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CLC number: TN385
On-line Access: 2017-09-08
Received: 2016-02-25
Revision Accepted: 2016-07-10
Crosschecked: 2017-08-06
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Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs
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Ying-hui Zhong, Shu-xiang Sun, Wen-bin Wong, Hai-li Wang, Xiao-ming Liu, Zhi-yong Duan, Peng Ding, Zhi Jin. Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(8): 1180-1185.
@article{title="Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs",
author="Ying-hui Zhong, Shu-xiang Sun, Wen-bin Wong, Hai-li Wang, Xiao-ming Liu, Zhi-yong Duan, Peng Ding, Zhi Jin",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="18",
number="8",
pages="1180-1185",
year="2017",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1601121"
}
%0 Journal Article
%T Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs
%A Ying-hui Zhong
%A Shu-xiang Sun
%A Wen-bin Wong
%A Hai-li Wang
%A Xiao-ming Liu
%A Zhi-yong Duan
%A Peng Ding
%A Zhi Jin
%J Frontiers of Information Technology & Electronic Engineering
%V 18
%N 8
%P 1180-1185
%@ 2095-9184
%D 2017
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1601121
TY - JOUR
T1 - Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs
A1 - Ying-hui Zhong
A1 - Shu-xiang Sun
A1 - Wen-bin Wong
A1 - Hai-li Wang
A1 - Xiao-ming Liu
A1 - Zhi-yong Duan
A1 - Peng Ding
A1 - Zhi Jin
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 18
IS - 8
SP - 1180
EP - 1185
%@ 2095-9184
Y1 - 2017
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1601121
Abstract: A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors (HEMTs). High etching-selectivity ratio of InGaAs to InAlAs material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide (H2O2). selective wet-etching is validated in the gate-recess process of InAlAs/InGaAs InP-based HEMTs, which proceeds and automatically stops at the InAlAs barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAlAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. digital wet-etching is repeated for two cycles with about 3 nm InAlAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic transconductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.
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