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CLC number: TN402; TN47
On-line Access: 2010-06-02
Received: 2009-06-28
Revision Accepted: 2009-12-22
Crosschecked: 2010-05-04
Cited: 2
Clicked: 7681
Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer
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Di Li, Yin-tang Yang, Jiang-an Wang, Bing Li, Qiang Long, Jary Wei, Nai-di Wang, Lei Wang, Qian-kun Liu, Da-long Zhang. Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer[J]. Journal of Zhejiang University Science C, 2010, 11(6): 444-449.
@article{title="Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer",
author="Di Li, Yin-tang Yang, Jiang-an Wang, Bing Li, Qiang Long, Jary Wei, Nai-di Wang, Lei Wang, Qian-kun Liu, Da-long Zhang",
journal="Journal of Zhejiang University Science C",
volume="11",
number="6",
pages="444-449",
year="2010",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C0910381"
}
%0 Journal Article
%T Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer
%A Di Li
%A Yin-tang Yang
%A Jiang-an Wang
%A Bing Li
%A Qiang Long
%A Jary Wei
%A Nai-di Wang
%A Lei Wang
%A Qian-kun Liu
%A Da-long Zhang
%J Journal of Zhejiang University SCIENCE C
%V 11
%N 6
%P 444-449
%@ 1869-1951
%D 2010
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C0910381
TY - JOUR
T1 - Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer
A1 - Di Li
A1 - Yin-tang Yang
A1 - Jiang-an Wang
A1 - Bing Li
A1 - Qiang Long
A1 - Jary Wei
A1 - Nai-di Wang
A1 - Lei Wang
A1 - Qian-kun Liu
A1 - Da-long Zhang
J0 - Journal of Zhejiang University Science C
VL - 11
IS - 6
SP - 444
EP - 449
%@ 1869-1951
Y1 - 2010
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C0910381
Abstract: A 19 mW highly integrated GPS receiver with a Σ;Δ; fractional-N synthesizer is presented in this paper. Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design. A high linearity low noise amplifier (LNA) is integrated into the chip. The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package. The chip consumes 19 mW (LNA1 excluded) and the LNA1 6.3 mW. Measured performances are: noise figure<2 dB, channel gain=108 dB (LNA1 included), image rejection>36 dB, and −108 dBc/Hz @ 1 MHz phase noise offset from the carrier. The carrier noise ratio (C/N) can reach 41 dB at an input power of −130 dBm. The chip operates over a temperature range of [−40, 120] °C and ±5% tolerance over the CMOS technology process.
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