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Frontiers of Information Technology & Electronic Engineering

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Efficient and optimized approximate GDI full adders based on DT-CNTFETs for specific least significant bits

Author(s): Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, Nabiollah SHIRI
Affiliation(s): Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran; more
Corresponding email(s): H.ghasemian@sutech.ac.ir
Key Words: CNTFETs; Optimization algorithms; NSGA-II; Gate-diffusion-input (GDI); Approximate computing

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Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, Nabiollah SHIRI. Efficient and optimized approximate GDI full adders based on DT-CNTFETs for specific least significant bits[J]. Frontiers of Information Technology & Electronic Engineering , 1998, -1(15): .

@article{title="Efficient and optimized approximate GDI full adders based on DT-CNTFETs for specific least significant bits",
author="Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, Nabiollah SHIRI",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="-1",
number="-1",
pages="",
year="1998",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2200077"
}

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%J Frontiers of Information Technology & Electronic Engineering
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Abstract
Chinese Summary
Academic Network
Reviewer Comment

Abstract: Carbon nanotube field-effect transistors (CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing (AC)-based error-resilient digital circuits. Therefore, in this paper, CNTFET technology and the gate diffusion input (GDI) technique are merged, and three new approximate-based full adders (FAs) are presented with 6, 6, and 8 transistors. The nondominated sorting-based genetic algorithm II (NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits' improvement by approximately 50% in terms of power-delay-product (PDP) at the cost of area occupation. The Monte Carlo method (MCM) and 32 nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process, in which the higher stability of the proposed circuits compared to the literature is observed. The dynamic-threshold (DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance values and error metrics of the proposed circuits nominate them for the least significant bits (LSBs) parts of more complex arithmetic circuits such as multipliers.

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