Affiliation(s):
Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran;
moreAffiliation(s): Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran; School of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran; Department of Electrical and Electronic Engineering, Shiraz University of Technology, Shiraz, Iran;
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Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, Nabiollah SHIRI. Efficient and optimized approximate GDI full adders based on DT-CNTFETs for specific least significant bits[J]. Frontiers of Information Technology & Electronic Engineering , 1998, -1(15): .
@article{title="Efficient and optimized approximate GDI full adders based on DT-CNTFETs for specific least significant bits", author="Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, Nabiollah SHIRI", journal="Frontiers of Information Technology & Electronic Engineering", volume="-1", number="-1", pages="", year="1998", publisher="Zhejiang University Press & Springer", doi="10.1631/FITEE.2200077" }
%0 Journal Article %T Efficient and optimized approximate GDI full adders based on DT-CNTFETs for specific least significant bits %A Ayoub SADEGHI %A Razieh GHASEMI %A Hossein GHASEMIAN %A Nabiollah SHIRI %J Frontiers of Information Technology & Electronic Engineering %V -1 %N -1 %P %@ 1869-1951 %D 1998 %I Zhejiang University Press & Springer
TY - JOUR T1 - Efficient and optimized approximate GDI full adders based on DT-CNTFETs for specific least significant bits A1 - Ayoub SADEGHI A1 - Razieh GHASEMI A1 - Hossein GHASEMIAN A1 - Nabiollah SHIRI J0 - Frontiers of Information Technology & Electronic Engineering VL - -1 IS - -1 SP - EP - %@ 1869-1951 Y1 - 1998 PB - Zhejiang University Press & Springer ER -
Abstract: Carbon nanotube field-effect transistors (CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing (AC)-based error-resilient digital circuits. Therefore, in this paper, CNTFET technology and the gate diffusion input (GDI) technique are merged, and three new approximate-based full adders (FAs) are presented with 6, 6, and 8 transistors. The nondominated sorting-based genetic algorithm II (NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits' improvement by approximately 50% in terms of power-delay-product (PDP) at the cost of area occupation. The Monte Carlo method (MCM) and 32 nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process, in which the higher stability of the proposed circuits compared to the literature is observed. The dynamic-threshold (DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance values and error metrics of the proposed circuits nominate them for the least significant bits (LSBs) parts of more complex arithmetic circuits such as multipliers.
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