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Journal of Zhejiang University SCIENCE A

ISSN 1673-565X(Print), 1862-1775(Online), Monthly

A low-power high-throughput link splitting router for NoCs

Abstract: In this paper, we propose a technique for lowering the latency of the communication in a NoC (network on chip). The technique, which can support two qualities of service (QoS), i.e., the guaranteed throughput (GT) and best effort (BE), is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the 1-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.

Key words: Low-power, Latency, Throughput, Network on chip (NoC), Delay-insensitive, Router


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DOI:

10.1631/jzus.A0720117

CLC number:

TN402

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Received:

2007-12-12

Revision Accepted:

2008-04-24

Crosschecked:

2008-11-16

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