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Frontiers of Information Technology & Electronic Engineering
ISSN 2095-9184 (print), ISSN 2095-9230 (online)
2015 Vol.16 No.8 P.700-706
Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
Abstract: A multi-stage dual replica bit-line delay (MDRBD) technique is proposed for reducing access time by suppressing the sense-amplifier enable (SAE) timing variation of low voltage static random-access memory (SRAM) applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-line (RBL) capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology (Taiwan Semiconductor Manufacturing Company, Taiwan).
Key words: Process-variation-robust, Sense amplifier (SA), Replica bit-line (RBL) delay, Timing variation
创新点：同时采用多级和双复制位线技术，充分发挥两者在降低控制时序变化方面的优点，取得整体上的改进。
方法：首先，分析现有复制位线延迟技术，从统计学角度对各技术之间的关系进行分析，进而提出一种基于多级双复制位线延迟技术的控制时序产生电路（图5）。然后，针对所提电路与现有技术在最差条件下进行蒙特卡洛仿真对比，得出所提技术在最差工作条件下，与现有技术相比具有更好的鲁棒性（图8）。最后在电压、工艺角以及温度分别变化时，对所提电路设计与现有的电路进行性能对比,得出在工艺、电压及温度变化时，所提电路具有更好的稳定性（图9-11）。
结论：针对低电压SRAM灵敏放大器控制时序在工艺、电压以及温度变化产生的波动，提出一种多级双复制位线延迟技术，实现进一步降低灵敏放大器控制时序波动的效果。
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DOI:
10.1631/FITEE.1400439
CLC number:
TN43
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On-line Access:
2024-08-27
Received:
2023-10-17
Revision Accepted:
2024-05-08
Crosschecked:
2015-07-20