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Frontiers of Information Technology & Electronic Engineering
ISSN 2095-9184 (print), ISSN 2095-9230 (online)
2025 Vol.26 No.10 P.2041-2063
Effective fault detection in M3D ICs: a cluster-based BIST for enhanced inter-layer via fault coverage
Abstract: Monolithic three-dimensional integrated circuits (M3D ICs) have emerged as an innovative solution to overcome the limitations of traditional 2D scaling, offering improved performance, reduced power consumption, and enhanced functionality. Inter-layer vias (ILVs), crucial components of M3D ICs, provide vertical connectivity between layers but are susceptible to manufacturing and operational defects, such as stuck-at faults (SAFs), shorts, and opens, which can compromise system reliability. These challenges necessitate advanced built-in self-test (BIST) methodologies to ensure robust fault detection and localization while minimizing the testing overhead. In this paper, we introduce a novel BIST architecture tailored to efficiently detect ILV defects, particularly in irregularly positioned ILVs, and approximately localize them within clusters, using a walking pattern approach. In the proposed BIST framework, ILVs are grouped according to the probability of fault occurrence, enabling efficient detection of all SAFs and bridging faults (BFs) and most multiple faults within each cluster. This strategy empowers designers to fine-tune fault coverage, localization precision, and test duration to meet specific design requirements. The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters. The method also enhances efficiency in terms of area and hardware utilization, particularly for larger circuit benchmarks. For instance, in the LU32PEENG benchmark, where ILVs are divided into 64 clusters, the power, area, and hardware overheads are minimized to 0.82%, 1.03%, and 1.14%, respectively.
Key words: Monolithic three-dimensional integrated circuits (M3D ICs); Inter-layer vias (ILVs); Built-in self-test (BIST); Fault detection and localization
1库尔德斯坦大学电子与通信工程系，伊朗萨南达季市，90210
2伊尔默瑙工业大学计算机体系结构与嵌入式系统系，德国伊尔默瑙市，98693
摘要：单片三维集成电路（M3D IC）作为克服传统二维器件缩放限制的一种创新解决方案，能够提升性能、降低功耗、增强功能。作为M3D IC中的重要组件，层间通孔（ILV）可实现层间垂直连接，但其易在制造及运行过程中出现故障，如阻塞（SAF）、短路、开路等，进而影响系统可靠性。上述问题亟需采用先进的内建自测（BIST）方法，实现高效故障检测与定位，同时降低测试开销。本文提出一种新型BIST结构，能够高效检测ILV故障，尤其针对非规则分布的ILV，并基于步进模式方法实现簇内近似故障定位。在所提出的BIST框架中，根据故障发生的概率将ILV分成若干簇，以实现对所有SAF和桥接故障（BF）以及大部分多重故障的高效检测。该策略使设计者能够对故障覆盖率、定位精度、测试时间进行微调，以满足特定设计要求。新的BIST方法解决了现有方案的一个关键缺陷，即通过引入多簇ILV结构，显著减少了测试配置数量与总体测试时间。该方法还提高了区域和硬件利用率，尤其适用于大规模电路基准测试。例如，在LU32PEENG基准测试中，将ILV划分为64个簇后，功耗、面积、硬件开销分别降低0.82%、1.03%和1.14%。
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DOI:
10.1631/FITEE.2401094
CLC number:
TN407
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On-line Access:
2025-11-17
Received:
2024-12-26
Revision Accepted:
2025-06-24
Crosschecked:
2025-11-18