|
|
Journal of Zhejiang University SCIENCE A
ISSN 1673-565X(Print), 1862-1775(Online), Monthly
2004 Vol.5 No.9 P.1102-1105
A front-end automation tool supporting design, verification and reuse of SOC
Abstract: This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
Key words: System-On-Chip, Verilog, HDL, Verification, Reuse
References:
Open peer comments: Debate/Discuss/Question/Opinion
<1>
Pratik<protik.seeker@gmail.com>
2010-10-15 04:17:23
yea even I can't download. Would be nice if u can check the link
Thanks
DOI:
10.1631/jzus.2004.1102
CLC number:
TN402
Download Full Text:
Downloaded:
3952
Clicked:
10178
Cited:
1
On-line Access:
2024-08-27
Received:
2023-10-17
Revision Accepted:
2024-05-08
Crosschecked: