Abstract: This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase accessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal testers. SR DfT is an oscillation-based wrapper compatible with digital embedded core-based SoC test methodologies. The impact of the optimized oscillation-based wrapper design on MS SoC testing is evaluated in two directions: area and test time. Experimental results are presented for several SoCs from the ITC’02 test benchmarks with inclusion of eight analog filters.

Key words: Scalable design for testability (DfT), Reconfigurable architecture, Embedded A/MS testing, Modular testing, Built-in self test (BIST)

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