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CLC number: TN918

On-line Access: 2013-08-02

Received: 2012-12-22

Revision Accepted: 2013-04-22

Crosschecked: 2013-07-12

Cited: 2

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Citations:  Bibtex RefMan EndNote GB/T7714

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Journal of Zhejiang University SCIENCE C 2013 Vol.14 No.8 P.642-651


A 10 Gbps in-line network security processor based on configurable hetero-multi-cores

Author(s):  Yun Niu, Li-ji Wu, Yang Liu, Xiang-min Zhang, Hong-yi Chen

Affiliation(s):  National Laboratory for Information Science and Technology, Tsinghua University, Beijing 100084, China; more

Corresponding email(s):   niuy08@mails.tsinghua.edu.cn, lijiwu@mail.tsinghua.edu.cn

Key Words:  10 Gbps Ethernet, Network security processor (NSP), Internet Protocol Security (IPSec), Crossbar

Yun Niu, Li-ji Wu, Yang Liu, Xiang-min Zhang, Hong-yi Chen. A 10 Gbps in-line network security processor based on configurable hetero-multi-cores[J]. Journal of Zhejiang University Science C, 2013, 14(8): 642-651.

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publisher="Zhejiang University Press & Springer",

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DOI - 10.1631/jzus.C1200370

This paper deals with an in-line network security processor (NSP) design that implements the internet Protocol Security (IPSec) protocol processing for the 10 Gbps Ethernet. The 10 Gbps high speed data transfer, the IPSec processing including the crypto-operation, the database query, and IPSec header processing are integrated in the design. The in-line NSP is implemented using 65 nm CMOS technology and the layout area is 2.5 mm×3 mm with 360 million gates. A configurable crossbar data transfer skeleton implementing an iSLIP scheduling algorithm is proposed, which enables simultaneous data transfer between the heterogeneous multiple cores. There are, in addition, a high speed input/output data buffering mechanism and design of high performance hardware structures for modules, wherein the transfer efficiency and the resource utilization are maximized and the IPSec protocol processing achieves 10 Gbps line speed. A high speed and low power hardware look-up method is proposed, which effectively reduces the area and power dissipation. The post simulation results demonstrate that the design gives a peak throughput for the Authentication Header (AH) transport mode of 10.06 Gbps with the average test packet length of 512 bytes under the clock rate of 250 MHz, and power dissipation less than 1 W is obtained. An FPGA prototype is constructed to verify the function of the design. A test bench is being set up for performance and function verification.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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