CLC number: TN43
On-line Access: 2014-12-05
Received: 2014-03-14
Revision Accepted: 2014-06-10
Crosschecked: 2014-11-06
Cited: 0
Clicked: 7255
Ting Guo, Zhi-qun Li, Qin Li, Zhi-gong Wang. A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers[J]. Journal of Zhejiang University Science C, 2014, 15(12): 1200-1210.
@article{title="A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers",
author="Ting Guo, Zhi-qun Li, Qin Li, Zhi-gong Wang",
journal="Journal of Zhejiang University Science C",
volume="15",
number="12",
pages="1200-1210",
year="2014",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1400091"
}
%0 Journal Article
%T A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers
%A Ting Guo
%A Zhi-qun Li
%A Qin Li
%A Zhi-gong Wang
%J Journal of Zhejiang University SCIENCE C
%V 15
%N 12
%P 1200-1210
%@ 1869-1951
%D 2014
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1400091
TY - JOUR
T1 - A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers
A1 - Ting Guo
A1 - Zhi-qun Li
A1 - Qin Li
A1 - Zhi-gong Wang
J0 - Journal of Zhejiang University Science C
VL - 15
IS - 12
SP - 1200
EP - 1210
%@ 1869-1951
Y1 - 2014
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1400091
Abstract: A 37 GHz wide-band programmable divide-by-N frequency divider (FD) composed of a divide-by-2 divider (acting as the first stage) and a divider with a division ratio range of 273–330 (acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider (with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic (DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as −20 dBm at 32 GHz and the phase noise at 37 GHz is less than −130 dBc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 mW at a supply voltage of 1.2 V and occupies an area of only 730 μm ×475 μm.
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