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CLC number: TN453
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2020-10-27
Cited: 0
Clicked: 5352
Citations: Bibtex RefMan EndNote GB/T7714
https://orcid.org/0000-0002-8683-9880
A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP
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Wei Zou, Daming Ren, Xuecheng Zou. A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(2): 251-261.
@article{title="A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP",
author="Wei Zou, Daming Ren, Xuecheng Zou",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="22",
number="2",
pages="251-261",
year="2021",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1900653"
}
%0 Journal Article
%T A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP
%A Wei Zou
%A Daming Ren
%A Xuecheng Zou
%J Frontiers of Information Technology & Electronic Engineering
%V 22
%N 2
%P 251-261
%@ 2095-9184
%D 2021
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1900653
TY - JOUR
T1 - A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP
A1 - Wei Zou
A1 - Daming Ren
A1 - Xuecheng Zou
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 22
IS - 2
SP - 251
EP - 261
%@ 2095-9184
Y1 - 2021
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1900653
Abstract: A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems, in which the scheme adopts low phase noise voltage-controlled oscillators (VCOs) and a charge pump (CP) with reduced current mismatch. VCOs that determine the out-band phase noise of a phase-locked loop (PLL) based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor. A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors. Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs. Fabricated in a TSMC 0.18-µm CMOS process, the prototype operates from 0.20 to 2.43 GHz. The PLL synthesizer achieves an in-band phase noise of −96.8 dBc/Hz and an out-band phase noise of −122.8 dBc/Hz at the 2.43-GHz carrier. The root-mean-square jitter is 1.2 ps under the worst case, and the measured reference spurs are less than −65.3 dBc. The current consumption is 15.2 mA and the die occupies 850 µm×920 µm.
[1]Berny AD, Niknejad AM, Meyer RG, 2005. A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration. IEEE J Sol-State Circ, 40(4):909-917.
[2]Chang HH, Wang PY, Zhan JHC, et al., 2008. A fractional spur-free ADPLL with loop-gain calibration and phase-noise cancellation for GSM/GPRS/EDGE. IEEE Int Conf on Solid-State Circuits, p.200-201, 606.
[3]Chang WS, Huang PC, Lee TC, 2014. A fractional-N divider-less phase-locked loop with a subsampling phase detector. IEEE J Sol-State Circ, 49(12):2964-2975.
[4]Chiu WH, Chang TS, Lin TH, 2009. A charge pump current missmatch calibration technique for ΔΣ fractional-N PLLs in 0.18-μm CMOS. IEEE Asian Solid-State Circuits Conf, p.73-76.
[5]de Muer B, Steyaert MSJ, 2002. A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800. IEEE J Sol-State Circ, 37(7):835-844.
[6]Deng W, Musa A, Okada K, et al., 2012. A 0.38 mm2, 10 MHz–6.6 GHz quadrature frequency synthesizer using fractional-N injection-locked technique. IEEE Asian Solid State Circuits Conf, p.353-356.
[7]Deng W, Hara S, Musa A, et al., 2014. A compact and low-power fractionally injection-locked quadrature frequency synthesizer using a self-synchronized gating injection technique for software-defined radios. IEEE J Sol-State Circ, 49(9):1984-1994.
[8]Gao X, Klumperink EAM, Socci G, et al., 2010. Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector. IEEE J Sol-State Circ, 45(9):1809-1821.
[9]Hara S, Okada K, Matsuzawa A, 2010. 10 MHz to 7 GHz quadrature signal generation using a divide-by-4/3, -3/2, -5/3, -2, -5/2, -3, -4, and -5 injection-locked frequency divider. Symp on VLSI Circuits, p.51-52.
[10]Hedayati H, Bakkaloglu B, Khalil W, 2009. A 1 MHz-bandwidth type-I ΔΣ fractional-N synthesizer for WiMAX applications. IEEE Int Conf on Solid-State Circuits, p.390-391, 391a.
[11]Hsu CM, Straayer MZ, Perrott MH, 2008. A low-noise, wide-BW 3.6 GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation. IEEE Int Conf on Solid-State Circuits, p.340-617.
[12]Huh H, Koo Y, Lee KY, et al., 2005. Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer. IEEE J Sol-State Circ, 40(11):2228-2236.
[13]Italia A, Ippolito CM, Palmisano G, 2012. A 1-mW 1.13–1.9 GHz CMOS LC VCO using shunt-connected switched-coupled inductors. IEEE Trans Circ Syst I, 59(6):1145-1155.
[14]Jeong CH, Kim KY, Kwon CK, et al., 2013. Digital calibration technique using a signed counter for charge pump mismatch in phase-locked loops. IET Circ Dev Syst, 7(6):313-318.
[15]Liang CF, Chen SH, Liu SI, 2008. A digital calibration technique for charge pumps in phase-locked systems. IEEE J Sol-State Circ, 43(2):390-398.
[16]Liao DY, Wang HC, Dai FF, et al., 2017. An 802.11a/b/g/n digital fractional-N PLL with automatic TDC linearity calibration for spur cancellation. IEEE J Sol-State Circ, 52(5):1210-1220.
[17]Lim CC, Ramiah H, Yin J, et al., 2016. A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM. IEEE Int Symp on Circuits and Systems, p.2759-2762.
[18]Mahmoud A, Fanori L, Mattsson T, et al., 2016. A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process. Analog Integr Circ Signal Process, 88(3):391-399.
[19]Narayanan AT, Katsuragi M, Kimura K, et al., 2016. A fractional-N sub-sampling PLL using a pipelined phase-interpolator with an FoM of −250 dB. IEEE J Sol-State Circ, 51(7):1630-1640.
[20]Nuzzo P, Vengattaramane K, Ingels M, et al., 2009. A 0.1–5 GHz dual-VCO software-defined frequency synthesizer in 45 nm digital CMOS. Proc IEEE Radio Frequency Integrated Circuits Symp, p.321-324.
[21]Osmany SA, Herzel F, Scheytt JC, 2010. An integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz frequency synthesizer for software-defined radio applications. IEEE J Sol-State Circ, 45(9):1657-1668.
[22]Pamarti S, Jansson L, Galton I, 2004. A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation. IEEE J Sol-State Circ, 39(1):49-62.
[23]Ruippo P, Lehtonen TA, Tchamov NT, 2010. An UMTS and GSM low phase noise inductively tuned LC VCO. IEEE Microw Wirel Compon Lett, 20(3):163-165.
[24]Sharkia A, Mirabbasi S, Shekhar S, 2018. A 0.01 mm2 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with –254 dB FOM. Proc IEEE Int Conf on Solid-State Circuits, p.256-258.
[25]Temporiti E, Albasini G, Bietti I, et al., 2004. A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications. IEEE J Sol-State Circ, 39(9):1446-1454.
[26]Wang KJ, Swaminathan A, Galton I, 2008. Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz fractional-N PLL. IEEE J Sol-State Circ, 43(12):2787-2797.
[27]Wu Y, Shahmohammadi M, Chen Y, et al., 2017. A 3.5–6.8-GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΣΔ-TDC for low in-band phase noise. IEEE J Sol-State Circ, 52(7):1885-1903.
[28]Yoon H, Lee Y, Kim JJ, et al., 2014. A wideband dual-mode LC-VCO with a switchable gate-biased active core. IEEE Trans Circ Syst II, 61(5):289-293.
[29]Yu SA, Baeyens Y, Weiner J, et al., 2011. A single-chip 125-MHz to 32-GHz signal source in 0.18-μm SiGe BiCMOS. IEEE J Sol-State Circ, 46(3):598-614.
[30]Yu YH, Chen JH, Chen YJE, 2018. A wideband 90-nm CMOS phase-locked loop with current mismatch calibration for spur reduction. IEEE Conf on Asia-Pacific Microwave, p.1504-1506.
[31]Zhang Z, Zhu G, Yue CP, 2019. 30.8 A 0.65V 12-to-16GHz sub-sampling PLL with 56.4fsrms integrated jitter and −256.4dB FoM. IEEE Int Conf on Solid-State Circuits, p.488-490.
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