CLC number: TP333.5
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2023-02-06
Cited: 0
Clicked: 1929
Citations: Bibtex RefMan EndNote GB/T7714
Jin XUE, Renhai CHEN, Tianyu WANG, Zili SHAO. SoftSSD: enabling rapid flash firmware prototyping for solid-state drives
@article{title="SoftSSD: enabling rapid flash firmware prototyping for solid-state drives
author="Jin XUE, Renhai CHEN, Tianyu WANG, Zili SHAO",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="24",
number="5",
pages="659-674",
year="2023",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2200456"
}
%0 Journal Article
%T SoftSSD: enabling rapid flash firmware prototyping for solid-state drives
%A Jin XUE
%A Renhai CHEN
%A Tianyu WANG
%A Zili SHAO
%J Frontiers of Information Technology & Electronic Engineering
%V 24
%N 5
%P 659-674
%@ 2095-9184
%D 2023
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2200456
TY - JOUR
T1 - SoftSSD: enabling rapid flash firmware prototyping for solid-state drives
A1 - Jin XUE
A1 - Renhai CHEN
A1 - Tianyu WANG
A1 - Zili SHAO
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 24
IS - 5
SP - 659
EP - 674
%@ 2095-9184
Y1 - 2023
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2200456
Abstract: Recently, solid-state drives (SSDs) have been used in a wide range of emerging data processing systems. Essentially, an SSD is a complex embedded system that involves both hardware and software design. For the latter, firmware modules such as the flash translation layer (FTL) orchestrate internal operations and flash management, and are crucial to the overall input/output performance of an SSD. Despite the rapid development of new SSD features in the market, the research of flash firmware has been mostly based on simulations due to the lack of a realistic and extensible SSD development platform. In this paper, we propose SoftSSD, a software-oriented SSD development platform for rapid flash firmware prototyping. The core of SoftSSD is a novel framework with an event-driven programming model. With the programming model, new FTL algorithms can be implemented and integrated into a full-featured flash firmware in a straightforward way. The resulting flash firmware can be deployed and evaluated on a hardware development board, which can be connected to a host system via peripheral component interconnect express and serve as a normal non-volatile memory express SSD. Different from existing hardware-oriented development platforms, SoftSSD implements the majority of SSD components (e.g., host interface controller) in software, so that data flows and internal states that were once confined in the hardware can now be examined with a software debugger, providing the observability and extensibility that are critical to the rapid prototyping and research of flash firmware. We describe the programming model and hardware design of SoftSSD. We also perform experiments with real application workloads on a prototype board to demonstrate the performance and usefulness of SoftSSD, and release the open-source code of SoftSSD for public access.
[1]Belson B, Holdsworth J, Xiang W, et al., 2019. A survey of asynchronous programming using coroutines in the Internet of Things and embedded systems. ACM Trans Embed Comput Syst, 18(3):21.
[2]Bjørling M, González J, Bonnet P, 2017. LightNVM: the Linux open-channel SSD subsystem. Proc 15th USENIX Conf on File and Storage Technologies, p.359-373.
[3]Boukhobza J, Rubini S, Chen RH, et al., 2017. Emerging NVM: a survey on architectural integration and research challenges. ACM Trans Des Autom Electron Syst, 23(2):14.
[4]Conway ME, 1963. Design of a separable transition-diagram compiler. Commun ACM, 6(7):396-408.
[5]Gao CM, Shi L, Zhao MY, et al., 2014. Exploiting parallelism in I/O scheduling for access conflict minimization in flash-based solid state drives. Proc 30th Symp on Mass Storage Systems and Technologies, p.1-11.
[6]Gupta A, Kim Y, Urgaonkar B, 2009. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. ACM SIGARCH Comput Archit News, 37(1):229-240.
[7]He J, Kannan S, Arpaci-Dusseau AC, et al., 2017. The unwritten contract of solid state drives. Proc 12th European Conf on Computer Systems, p.127-144.
[8]Ho KC, Fang PC, Li HP, et al., 2013. A 45 nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. IEEE Int Solid-State Circuits Conf, p.222-223.
[9]Hu Y, Jiang H, Feng D, et al., 2011. Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity. Proc Int Conf on Supercomputing, p.96-107.
[10]Jung M, Choi W, Gao SW, et al., 2016. NANDFlashSim: high-fidelity, microarchitecture-aware NAND flash memory simulation. ACM Trans Storage, 12(2):6.
[11]Jung M, Zhang J, Abulila A, et al., 2018. SimpleSSD: modeling solid state drives for holistic system simulation. IEEE Comput Archit Lett, 17(1):37-41.
[12]Kim Y, Tauras B, Gupta A, et al., 2009. FlashSim: a simulator for NAND flash-based solid-state drives. Proc 1st Int Conf on Advances in System Simulation, p.125-131.
[13]Kwak J, Lee S, Park K, et al., 2020. Cosmos+ OpenSSD: rapid prototype for flash storage systems. ACM Trans Storage, 16(3):15.
[14]Lee G, Shin S, Song W, et al., 2019. Asynchronous I/O stack: a low-latency kernel I/O stack for ultra-low latency SSDs. USENIX Annual Technical Conf, p.603-616.
[15]Li HC, Hao MZ, Tong MH, et al., 2018. The case of FEMU: cheap, accurate, scalable and extensible flash emulator. Proc 16th USENIX Conf on File and Storage Technologies, p.83-90.
[16]Li S, Zhang T, 2010. Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding. IEEE Trans Very Large Scale Integr (VLSI) Syst, 18(10):1412-1420.
[17]Lu LY, Pillai TS, Arpaci-Dusseau AC, et al., 2016. WiscKey: separating keys from values in SSD-conscious storage. Proc 14th USENIX Conf on File and Storage Technologies, p.133-148.
[18]Lu YY, Shu JW, Zheng WM, 2013. Extending the lifetime of flash-based storage through reducing write amplification from file systems. Proc 11th USENIX Conf on File and Storage Technologies, p.257-270.
[19]Ma CL, Wang Y, Shen ZY, et al., 2020. MNFTL: an efficient flash translation layer for MLC NAND flash memory. ACM Trans Des Autom Electron Syst, 25(6):50.
[20]Moura ALD, Ierusalimschy R, 2009. Revisiting coroutines. ACM Trans Program Lang Syst, 31(2):6.
[21]Shi L, Di YJ, Zhao MY, et al., 2016. Exploiting process variation for write performance improvement on NAND flash memory storage systems. IEEE Trans Very Large Scale Integr (VLSI) Syst, 24(1):334-337.
[22]Tavakkol A, Gómez-Luna J, Sadrosadati M, et al., 2018. MQSim: a framework for enabling realistic studies of modern multi-queue SSD devices. Proc 16th USENIX Conf on File and Storage Technologies, p.49-66.
[23]Wang S, Wu F, Lu Z, et al., 2017. Lifetime adaptive ECC in NAND flash page management. Design, Automation & Test in Europe Conf & Exhibition, p.1253-1256.
[24]Xue J, Chen R, Shao Z, 2022. SoftSSD: software-defined SSD development platform for rapid flash firmware prototyping. IEEE 40th Int Conf on Computer Design, p.602-609.
[25]Yang MC, Chang YM, Tsao CW, et al., 2014. Garbage collection and wear leveling for flash memory: past and future. Int Conf on Smart Computing, p.66-73.
[26]Yoo J, Won Y, Hwang J, et al., 2013. VSSIM: virtual machine based SSD simulator. Proc IEEE 29th Symp on Mass Storage Systems and Technologies, p.1-14.
[27]Zhang J, Kwon M, Swift M, et al., 2020. Scalable parallel flash firmware for many-core architectures. Proc 18th USENIX Conf on File and Storage Technologies, p.121-136.
Open peer comments: Debate/Discuss/Question/Opinion
<1>