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Abstract: The power optimization of ‍%29&ck%5B%5D=abstract&ck%5B%5D=keyword'>mixed polarity Reed‍;–;‍;muller (MPRM) logic circuits is a classic combinatorial optimization problem. Existing optimization approaches often suffer from slow convergence and a propensity to converge to local optima, limiting their effectiveness in achieving optimal power efficiency. First, we propose a novel multi-strategy fusion memetic algorithm (MFMA). MFMA integrates global exploration via the chimp optimization algorithm with local exploration using the coati optimization algorithm based on the optimal position learning and adaptive weight factor (COA-OLA), complemented by population management through truncation selection. Second, leveraging MFMA, we propose a power optimization approach for MPRM logic circuits that searches for the best polarity configuration to minimize circuit power. Experimental results based on Microelectronics Center of North Carolina (MCNC) benchmark circuits demonstrate significant improvements over existing power optimization approaches. MFMA achieves a maximum power saving rate of 72.30% and an average optimization rate of 43.37%; it searches for solutions faster and with higher quality, validating its effectiveness and superiority in power optimization.

一种基于MFMA的MPRM逻辑电路功耗优化方法

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