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On-line Access: 2024-08-27
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Co-design for an SoC embedded network controller
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Zou Lian-ying, Zou Xue-cheng. Co-design for an SoC embedded network controller[J]. Journal of Zhejiang University Science A, 2006, 7(4): 591-596.
@article{title="Co-design for an SoC embedded network controller",
author="Zou Lian-ying, Zou Xue-cheng",
journal="Journal of Zhejiang University Science A",
volume="7",
number="4",
pages="591-596",
year="2006",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.2006.A0591"
}
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T1 - Co-design for an SoC embedded network controller
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A1 - Zou Xue-cheng
J0 - Journal of Zhejiang University Science A
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DOI - 10.1631/jzus.2006.A0591
Abstract: With the development of Ethernet systems and the growing capacity of modern silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethernet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Internet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system’s throughput. Our simulation results showed that the maximum throughput of Ethernet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethernet, and that using only one chip can realize that many electronic devices access to the Internet directly and get high performance.
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