CLC number: TP391.9
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2023-01-04
Cited: 0
Clicked: 1694
Juan FANG, Sheng LIN, Huijing YANG, Yixiang XU, Xing SU. A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous system[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(7): 994-1006.
@article{title="A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous system",
author="Juan FANG, Sheng LIN, Huijing YANG, Yixiang XU, Xing SU",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="24",
number="7",
pages="994-1006",
year="2023",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2200449"
}
%0 Journal Article
%T A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous system
%A Juan FANG
%A Sheng LIN
%A Huijing YANG
%A Yixiang XU
%A Xing SU
%J Frontiers of Information Technology & Electronic Engineering
%V 24
%N 7
%P 994-1006
%@ 2095-9184
%D 2023
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2200449
TY - JOUR
T1 - A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous system
A1 - Juan FANG
A1 - Sheng LIN
A1 - Huijing YANG
A1 - Yixiang XU
A1 - Xing SU
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 24
IS - 7
SP - 994
EP - 1006
%@ 2095-9184
Y1 - 2023
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2200449
Abstract: When multiple central processing unit (CPU) cores and integrated graphics processing units (GPUs) share off-chip main memory, CPU and GPU applications compete for the critical memory resource. This causes serious resource competition and has a negative impact on the overall performance of the system. We describe the competition for shared-memory resources in a CPU-GPU heterogeneous multi-core architecture, and a shared-memory request scheduling strategy based on perceptual and predictive batch-processing is proposed. By sensing the CPU and GPU memory request conditions in the request buffer, the proposed scheduling strategy estimates the GPU latency tolerance and reduces mutual interference between CPU and GPU by processing CPU or GPU memory requests in batches. According to the simulation results, the scheduling strategy improves CPU performance by 8.53% and reduces mutual interference by 10.38% with low hardware complexity.
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