CLC number: TP183; TP302
On-line Access: 2022-04-22
Received: 2018-08-05
Revision Accepted: 2018-09-09
Crosschecked: 2018-10-10
Cited: 0
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Xiaobo Sharon Hu, Michael Niemier. Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt[J]. Frontiers of Information Technology & Electronic Engineering, 2018, 19(10): 1209-1223.
@article{title="Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt",
author="Xiaobo Sharon Hu, Michael Niemier",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="19",
number="10",
pages="1209-1223",
year="2018",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1800466"
}
%0 Journal Article
%T Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt
%A Xiaobo Sharon Hu
%A Michael Niemier
%J Frontiers of Information Technology & Electronic Engineering
%V 19
%N 10
%P 1209-1223
%@ 2095-9184
%D 2018
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1800466
TY - JOUR
T1 - Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt
A1 - Xiaobo Sharon Hu
A1 - Michael Niemier
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 19
IS - 10
SP - 1209
EP - 1223
%@ 2095-9184
Y1 - 2018
PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.1800466
Abstract: As moore's law based device scaling and accompanying performance scaling trends are slowing down, there is increasing interest in new technologies and computational models for fast and more energy-efficient information processing. Meanwhile, there is growing evidence that, with respect to traditional Boolean circuits and von Neumann processors, it will be challenging for beyond-CMOS devices to compete with the CMOS technology. Exploiting unique characteristics of emerging devices, especially in the context of alternative circuit and architectural paradigms, has the potential to offer orders of magnitude improvement in terms of power, performance, and capability. To take full advantage of beyond-CMOS devices, cross-layer efforts spanning from devices to circuits to architectures to algorithms are indispensable. This study examines energy-efficient neural network accelerators for embedded applications in this context. Several deep neural network accelerator designs based on cross-layer efforts spanning from alternative device technologies, circuit styles, to architectures are highlighted. Application-level benchmarking studies are presented. The discussions demonstrate that cross-layer efforts indeed can lead to orders of magnitude gain towards achieving extreme-scale energy-efficient processing.
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