CLC number: TN402; TP37
On-line Access:
Received: 2005-03-20
Revision Accepted: 2005-08-12
Crosschecked: 0000-00-00
Cited: 0
Clicked: 5223
Xiao Zhi-bin, Liu Peng, Yao Ying-biao, Yao Qing-dong. Optimizing pipeline for a RISC processor with multimedia extension ISA[J]. Journal of Zhejiang University Science A, 2006, 7(2): 269-274.
@article{title="Optimizing pipeline for a RISC processor with multimedia extension ISA",
author="Xiao Zhi-bin, Liu Peng, Yao Ying-biao, Yao Qing-dong",
journal="Journal of Zhejiang University Science A",
volume="7",
number="2",
pages="269-274",
year="2006",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.2006.A0269"
}
%0 Journal Article
%T Optimizing pipeline for a RISC processor with multimedia extension ISA
%A Xiao Zhi-bin
%A Liu Peng
%A Yao Ying-biao
%A Yao Qing-dong
%J Journal of Zhejiang University SCIENCE A
%V 7
%N 2
%P 269-274
%@ 1673-565X
%D 2006
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.2006.A0269
TY - JOUR
T1 - Optimizing pipeline for a RISC processor with multimedia extension ISA
A1 - Xiao Zhi-bin
A1 - Liu Peng
A1 - Yao Ying-biao
A1 - Yao Qing-dong
J0 - Journal of Zhejiang University Science A
VL - 7
IS - 2
SP - 269
EP - 274
%@ 1673-565X
Y1 - 2006
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.2006.A0269
Abstract: The 32-bit extensible embedded processor RISC3200 originating from an RTL prototype core is intended for low-cost consumer multimedia products. In order to incorporate the reduced instruction set and the multimedia extension instruction set in a unifying pipeline, a scalable super-pipeline technique is adopted. Several other optimization techniques are proposed to boost the frequency and reduce the average CPI of the unifying pipeline. Based on a data flow graph (DFG) with delay information, the critical path of the pipeline stage can be located and shortened. This paper presents a distributed data bypass unit and a centralized pipeline control scheme for achieving lower CPI. Synthesis and simulation showed that the optimization techniques enable RISC3200 to operate at 200 MHz with an average CPI of 1.16. The core was integrated into a media SOC chip taped out in SMIC 0.18-micron technology. Preliminary testing result showed that the processor works well as we expected.
[1] Dasu, A., Panchanathan, S., 2002. A survey of media processing approaches. IEEE Transactions on Circuits and Systems for Video Technology, 12(8):633-645.
[2] Dutt, N., Choi, K., 2003. Configurable processors for embedded computing. IEEE Computer, 36(1):120-123.
[3] Ferreti, M., 2000. Multimedia Extensions in Super-pipelined Micro-architecture. A New Case for SIMD Processing? Proceeding of 5th IEEE Int. Workshop Computer Architectures for Machine Perception, p.249-258.
[4] Hennessy, J.L., Patterson, D.A., 2002. Computer Architecture: A Quantitative Approach, 3rd Edition. Elsevier Science Pte Ltd.
[5] Ishiwata, S., Yamakage, T., Tsuboi, Y., Shimazawa, T., Kitazawa, T., Michinaka, S., Yahagi, K., Takeda, H., Oue, A., Kodama, T., Matsumoto, N., Kamei, T., Miyamori, T., Ootomo, G., Matsui, M., 2003. A single-chip MPEG-2 codec based on customizable media embedded processor. IEEE Journal of Solid-State Circuits, 38(3):530-540.
[6] Lappalainen, V., Hamalaine, T.D., Liuha, P., 2002. Overview of research efforts on media ISA extensions and their usage in video decoding. IEEE Transactions on Circuits and Systems for Video Technology, 12(8):660-670.
[7] Lee, R.B., 1997. Multimedia Extensions for General-purpose Processors. Proceeding of IEEE Workshop Signal Processing Systems-Design and Implementation (SPIS’97), p.9-23.
[8] Liu, P., 2001. Hardware/software codesign for embedded RISC core. Proceedings of SPIE Media Processors, 4674:21-28.
[9] Liu, P., Wang, W.D., Xiao, Z.B., Lai, L.Y., Teng, Z.W., Yu, G.J., Yao, Y.B., Chen, K.M., Jiang, Z.D., Zhang, Y.X., Zhou, J., Cai, W.G., Zhai, Z.B., Shi, C., Yao, Q.D., 2005. MediaSOC: A System-on-Chip Architecture for Multimedia Application. IEEE International Workshop on VLSI Design and Video Technology (IWVDVT2005), Suzhou, China, p.161-164.
[10] Wu, H., Liu, P., Wang, W.D., Cai, Z., Yao, Q.D., 2004. Reconfigurable hardware/software cosimulation platform for media processor. Proceedings of SPIE, 5309:114-122.
[11] Yao, Y.B., Yao, Q.D., Liu, P., Xiao, Z.B., 2004. Embedded software optimization for MP3 decoder implemented on RISC core. IEEE Transactions on Consumer Electronics, 50(4):1244-1249.
Open peer comments: Debate/Discuss/Question/Opinion
<1>