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CLC number: TP302.7

On-line Access: 2011-11-30

Received: 2011-01-26

Revision Accepted: 2011-07-26

Crosschecked: 2011-11-04

Cited: 2

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Journal of Zhejiang University SCIENCE C 2011 Vol.12 No.12 P.976-989


Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture

Author(s):  Dan Wu, Xue-cheng Zou, Kui Dai, Jin-li Rao, Pan Chen, Zhao-xia Zheng

Affiliation(s):  Department of Electronic Science & Technology, Huazhong University of Science and Technology, Wuhan 430074, China

Corresponding email(s):   dandan58wu@gmail.com, josh.maxview@gmail.com

Key Words:  Fast Fourier transform (FFT), Multi-core, Parallel computing, SIMD

Dan Wu, Xue-cheng Zou, Kui Dai, Jin-li Rao, Pan Chen, Zhao-xia Zheng. Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture[J]. Journal of Zhejiang University Science C, 2011, 12(12): 976-989.

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%T Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture
%A Dan Wu
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%A Kui Dai
%A Jin-li Rao
%A Pan Chen
%A Zhao-xia Zheng
%J Journal of Zhejiang University SCIENCE C
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%P 976-989
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%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1100027

T1 - Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture
A1 - Dan Wu
A1 - Xue-cheng Zou
A1 - Kui Dai
A1 - Jin-li Rao
A1 - Pan Chen
A1 - Zhao-xia Zheng
J0 - Journal of Zhejiang University Science C
VL - 12
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EP - 989
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.C1100027

The fast Fourier transform (FFT) is a fundamental kernel of many computation-intensive scientific applications. This paper deals with an implementation of the FFT on the accelerator system, a heterogeneous multi-core architecture to accelerate computation-intensive parallel computing in scientific and engineering applications. The Engineering and Scientific Computation Accelerator (ESCA) consists of a control unit and a single instruction multiple data (SIMD) processing element (PE) array, in which PEs communicate with each other via a hierarchical two-level network-on-chip (NoC) with high bandwidth and low latency. We exploit the architecture features of ESCA to implement a parallel FFT algorithm efficiently. Experimental results show that both the proposed parallel FFT algorithm and the ESCA architecture are scalable. The 16-bit fixed-point parallel FFT performance of ESCA is compared with a published work to prove the superiority of the mapping algorithm and the hardware architecture. The floating-point parallel FFT performances of ESCA are evaluated and compared with those of the IBM Cell processor and GPU to demonstrate the computing power of the ESCA system for high performance applications.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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