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Journal of Zhejiang University SCIENCE A 2009 Vol.10 No.6 P.922-926

http://doi.org/10.1631/jzus.A0820803


Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach


Author(s):  Shervin VAKILI, Sied Mehdi FAKHRAIE, Siamak MOHAMMADI, Ali AHMADI

Affiliation(s):  School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran

Corresponding email(s):   sh.vakili@ece.ut.ac.ir

Key Words:  Fault tolerance, Multiprocessor system-on-chip (MPSoC), Genetic algorithm (GA), Adaptive task scheduling


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Shervin VAKILI, Sied Mehdi FAKHRAIE, Siamak MOHAMMADI, Ali AHMADI. Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach[J]. Journal of Zhejiang University Science A, 2009, 10(6): 922-926.

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Abstract: 
The evolvable multiprocessor (EvoMP), as a novel multiprocessor system-on-chip (MPSoC) machine with evolvable task decomposition and scheduling, claims a major feature of low-cost and efficient fault tolerance. Non-centralized control and adaptive distribution of the program among the available processors are two major capabilities of this platform, which remarkably help to achieve an efficient fault tolerance scheme. This letter presents the operational as well as architectural details of this fault tolerance scheme. In this method, when a processor becomes faulty, it will be eliminated of contribution in program execution in remaining run-time. This method also utilizes dynamic rescheduling capability of the system to achieve the maximum possible efficiency after processor reduction. The results confirm the efficiency and remarkable advantages of the proposed approach over common redundancy based techniques in similar systems.

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Reference

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[4] Manimaran, G., Murthy, C.S.R., 1998a. An efficient dynamic scheduling algorithm for multiprocessor real-time systems. IEEE Trans. Parall. Distrib. Syst., 9(3):312-319.

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[7] Obermaisser, R., Kraut, H., Salloum, C., 2008. A Transient-resilient System-on-a-chip Architecture with Support for On-chip and Off-chip TMR. Proc. Int. Dependable Computing Conf., p.123-134.

[8] Vakili, S., Fakhraie, S.M., Mohammadi, S., 2008. Designing an MPSoC Architecture with Run-time and Evolvable Task Decomposition and Scheduling: A Neural Network Case Study. 5th IEEE Int. Conf. on Innovations in Information Technology, p.106-110.

[9] Wolf, W., 2004. The Future of Multiprocessor Systems-on-chips. Proc. Int. Design Automation Conf., p.681-685.

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