Full Text:   <2652>

CLC number: TN4

On-line Access: 

Received: 2008-11-19

Revision Accepted: 2009-04-23

Crosschecked: 2009-04-29

Cited: 1

Clicked: 4449

Citations:  Bibtex RefMan EndNote GB/T7714

-   Go to

Article info.
1. Reference List
Open peer comments

Journal of Zhejiang University SCIENCE A 2009 Vol.10 No.6 P.922-926

http://doi.org/10.1631/jzus.A0820803


Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach


Author(s):  Shervin VAKILI, Sied Mehdi FAKHRAIE, Siamak MOHAMMADI, Ali AHMADI

Affiliation(s):  School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran

Corresponding email(s):   sh.vakili@ece.ut.ac.ir

Key Words:  Fault tolerance, Multiprocessor system-on-chip (MPSoC), Genetic algorithm (GA), Adaptive task scheduling


Share this article to: More <<< Previous Article|

Shervin VAKILI, Sied Mehdi FAKHRAIE, Siamak MOHAMMADI, Ali AHMADI. Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach[J]. Journal of Zhejiang University Science A, 2009, 10(6): 922-926.

@article{title="Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach",
author="Shervin VAKILI, Sied Mehdi FAKHRAIE, Siamak MOHAMMADI, Ali AHMADI",
journal="Journal of Zhejiang University Science A",
volume="10",
number="6",
pages="922-926",
year="2009",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.A0820803"
}

%0 Journal Article
%T Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach
%A Shervin VAKILI
%A Sied Mehdi FAKHRAIE
%A Siamak MOHAMMADI
%A Ali AHMADI
%J Journal of Zhejiang University SCIENCE A
%V 10
%N 6
%P 922-926
%@ 1673-565X
%D 2009
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A0820803

TY - JOUR
T1 - Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach
A1 - Shervin VAKILI
A1 - Sied Mehdi FAKHRAIE
A1 - Siamak MOHAMMADI
A1 - Ali AHMADI
J0 - Journal of Zhejiang University Science A
VL - 10
IS - 6
SP - 922
EP - 926
%@ 1673-565X
Y1 - 2009
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.A0820803


Abstract: 
The evolvable multiprocessor (EvoMP), as a novel multiprocessor system-on-chip (MPSoC) machine with evolvable task decomposition and scheduling, claims a major feature of low-cost and efficient fault tolerance. Non-centralized control and adaptive distribution of the program among the available processors are two major capabilities of this platform, which remarkably help to achieve an efficient fault tolerance scheme. This letter presents the operational as well as architectural details of this fault tolerance scheme. In this method, when a processor becomes faulty, it will be eliminated of contribution in program execution in remaining run-time. This method also utilizes dynamic rescheduling capability of the system to achieve the maximum possible efficiency after processor reduction. The results confirm the efficiency and remarkable advantages of the proposed approach over common redundancy based techniques in similar systems.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1] Barker, W., Halliday, D.M., Thoma, Y., Sanchez, E., Tempesti, G., Tyrrell, A., 2007. Fault tolerance using dynamic reconfiguration on the POEtic tissue. IEEE Trans. Evol. Comput., 11(5):666-684.

[2] Beitollahi, H., Deeconinick, G., 2006. Fault-tolerant Partitioning Scheduling Algorithms in Real-time Multi-processor Systems. Proc. Pacific Rim Symp. on Dependable Computing, p.296-304.

[3] Canham, R., Tyrrell, A., 2003. An Embryonic Array with Improved Efficiency and Fault Tolerance. Proc. NASA/DoD Conf. on Evolvable Hardware, p.265-272.

[4] Manimaran, G., Murthy, C.S.R., 1998a. An efficient dynamic scheduling algorithm for multiprocessor real-time systems. IEEE Trans. Parall. Distrib. Syst., 9(3):312-319.

[5] Manimaran, G., Murthy, C.S.R., 1998b. A fault-tolerant dynamic scheduling algorithm for multiprocessor real-time systems and its analysis. IEEE Trans. Parall. Distrib. Syst., 9(11):1137-1152.

[6] Martin, G., 2005. Overview of the MPSoC Design Challenge. Proc. Design and Automation Conf., p.274-279.

[7] Obermaisser, R., Kraut, H., Salloum, C., 2008. A Transient-resilient System-on-a-chip Architecture with Support for On-chip and Off-chip TMR. Proc. Int. Dependable Computing Conf., p.123-134.

[8] Vakili, S., Fakhraie, S.M., Mohammadi, S., 2008. Designing an MPSoC Architecture with Run-time and Evolvable Task Decomposition and Scheduling: A Neural Network Case Study. 5th IEEE Int. Conf. on Innovations in Information Technology, p.106-110.

[9] Wolf, W., 2004. The Future of Multiprocessor Systems-on-chips. Proc. Int. Design Automation Conf., p.681-685.

[10] Zomaya, A.Y., Ward, C., Macey, B., 1999. Genetic scheduling for parallel processor systems: comparative studies and performance issues. IEEE Trans. Parall. Distrib. Syst., 10(8):795-812.

Open peer comments: Debate/Discuss/Question/Opinion

<1>

Please provide your name, email address and a comment





Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - 2022 Journal of Zhejiang University-SCIENCE