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CLC number: TN91
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2010-12-08
Cited: 12
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A pipelined architecture for normal I/O order FFT
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Xue Liu, Feng Yu, Ze-ke Wang. A pipelined architecture for normal I/O order FFT[J]. Journal of Zhejiang University Science C, 2011, 12(1): 76-82.
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doi="10.1631/jzus.C1000234"
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Abstract: We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
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