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On-line Access: 2010-01-10

Received: 2010-07-02

Revision Accepted: 2010-10-11

Crosschecked: 2010-12-08

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Journal of Zhejiang University SCIENCE C 2011 Vol.12 No.1 P.76-82


A pipelined architecture for normal I/O order FFT

Author(s):  Xue Liu, Feng Yu, Ze-ke Wang

Affiliation(s):  Department of Instrument Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   liuxue0412@tom.com, osfengyu@zju.edu.cn

Key Words:  Fast Fourier transform (FFT), Single-path delay commutator (SDC), Pipelined FFT, Bit reverser

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Xue Liu, Feng Yu, Ze-ke Wang. A pipelined architecture for normal I/O order FFT[J]. Journal of Zhejiang University Science C, 2011, 12(1): 76-82.

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%DOI 10.1631/jzus.C1000234

T1 - A pipelined architecture for normal I/O order FFT
A1 - Xue Liu
A1 - Feng Yu
A1 - Ze-ke Wang
J0 - Journal of Zhejiang University Science C
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SP - 76
EP - 82
%@ 1869-1951
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.C1000234

We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

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