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CLC number: TN386.1

On-line Access: 2011-12-29

Received: 2011-04-07

Revision Accepted: 2011-06-19

Crosschecked: 2011-12-08

Cited: 3

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Journal of Zhejiang University SCIENCE C 2012 Vol.13 No.1 P.58-70

http://doi.org/10.1631/jzus.C1100090


An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling


Author(s):  Behrouz Afzal, Behzad Ebrahimi, Ali Afzali-Kusha, Massoud Pedram

Affiliation(s):  School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran, Department of Electrical Engineering, University of Southern California, Los Angeles, CA, USA

Corresponding email(s):   afzali@ut.ac.ir

Key Words:  Modeling, Nano-scale, Process variation, Read static noise margin (SNM), SRAM


Behrouz Afzal, Behzad Ebrahimi, Ali Afzali-Kusha, Massoud Pedram. An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling[J]. Journal of Zhejiang University Science C, 2012, 13(1): 58-70.

@article{title="An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling",
author="Behrouz Afzal, Behzad Ebrahimi, Ali Afzali-Kusha, Massoud Pedram",
journal="Journal of Zhejiang University Science C",
volume="13",
number="1",
pages="58-70",
year="2012",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1100090"
}

%0 Journal Article
%T An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling
%A Behrouz Afzal
%A Behzad Ebrahimi
%A Ali Afzali-Kusha
%A Massoud Pedram
%J Journal of Zhejiang University SCIENCE C
%V 13
%N 1
%P 58-70
%@ 1869-1951
%D 2012
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1100090

TY - JOUR
T1 - An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling
A1 - Behrouz Afzal
A1 - Behzad Ebrahimi
A1 - Ali Afzali-Kusha
A1 - Massoud Pedram
J0 - Journal of Zhejiang University Science C
VL - 13
IS - 1
SP - 58
EP - 70
%@ 1869-1951
Y1 - 2012
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1100090


Abstract: 
We propose an accurate model to describe the I-V characteristics of a sub-90-nm metal–oxide–semiconductor field-effect transistor (MOSFET) in the linear and saturation regions for fast analytical calculation of the current. The model is based on the BSIM3v3 model. Instead of using constant threshold voltage and early voltage, as is assumed in the BSIM3v3 model, we define these voltages as functions of the gate-source voltage. The accuracy of the model is verified by comparison with HSPICE for the 90-, 65-, 45-, and 32-nm CMOS technologies. The model shows better accuracy than the nth-power and BSIM3v3 models. Then, we use the proposed I-V model to calculate the read static noise margin (SNM) of nano-scale conventional 6T static random-access memory (SRAM) cells with high accuracy. We calculate the read SNM by approximating the inverter transfer voltage characteristic of the cell in the regions where vertices of the maximum square of the butterfly curves are placed. The results for the SNM are also in excellent agreement with those of the HSPICE simulation for 90-, 65-, 45-, and 32-nm technologies. Verification in the presence of process variations and negative bias temperature instability (NBTI) shows that the model can accurately predict the minimum supply voltage required for a target yield.

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Reference

[1]Agarwal, K., Nassif, S., 2008. The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies. IEEE Trans. Very Large Scale Integr. Syst., 16(1):86-97.

[2]Bhavnagarwala, A.J., Austin, B.L., Bowman, K.A., Meindl, J.D., 2000. A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst., 8(3):235-251.

[3]Bhavnagarwala, A.J., Tang, X., Meindl, J.D., 2001. The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Sol.-State Circ., 36(4):658-665.

[4]Calhoun, B., Chandrakasan, A., 2006. Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. IEEE J. Sol.-State Circ., 41(7):1673-1679.

[5]Chen, Q., Guha, A., Roy, K., 2007. An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. Proc. Int. Conf. on VLSI Design, p.615-620.

[6]Cheng, Y., Chan, M., Hui, K., Jeng, M.C., Liu, Z., Huang, J., Chen, K., Ko, P., Hu, C., 1995. BSIM3v3 MOSFET Model User’s Manual. Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA.

[7]Chiulli, R.M., 1999. Quantitative Analysis: an Introduction. Gordon and Breach Science Publishers, Amsterdam, the Netherlands.

[8]Hiroki, A., Yamate, A., Yamada, M., 2008. An Analytical MOSFET Model Including Gate Voltage Dependence of Channel Length Modulation Parameter for 20nm CMOS. Proc. Int. Conf. on Electrical and Computer Engineering, p.139-143.

[9]Hu, V.P.H., Wu, Y.S., Fan, M.L., Su, P., Chuang, C.T., 2009. Static noise margin of ultrathin-body SOI subthreshold SRAM cells—an assessment based on analytical solutions of Poisson’s equation. IEEE Trans. Electron Dev., 56(9):2120-2127.

[10]Kang, K., Kufluoglu, H., Roy, K., Alam, M.A., 2007. Impact of negative-bias temperature instability in nanoscale SRAM array: modeling and analysis. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst., 26(10):1770-1781.

[11]Li, Y., Hwang, C.H., Li, T.Y., 2009. Discrete-dopant-induced timing fluctuation and suppression in nanoscale CMOS circuit. IEEE Trans. Circ. Syst. II, 56(5):379-383.

[12]Lohstroh, J., Seevinck, E., DeGroot, J., 1983. Worst-case static noise margin criteria for logic circuits and their mathematical equivalence. IEEE J. Sol.-State Circ., 18(6):803-807.

[13]Morshed, T.H., Yang, W., Dunga, M.V., Xi, X., He, J., Liu, W., Kanyu, Cao, M., Jin, X., Ou, J.J., et al., 2009. BSIM4.6.4 MOSFET Model User’s Manual. Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA.

[14]Mukhopadhyay, S., Mahmoodi, H., Roy, K., 2005. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst., 24(12):1859-1880.

[15]Orshansky, M., Nassif, S., Boning, D., 2008. Design for Manufacturability and Statistical Design: a Constructive Approach. Springer Science+Business Media, LLC, New York, USA.

[16]Park, H., Song, S.C., Woo, S.H., Abu-Rahma, M.H., Ge, L., Kang, M.G., Han, B.M., Wang, J., Choi, R., Yang, J.W., et al., 2010. Accurate Projection of Vccmin by Modeling Dual Slope in FinFET Based SRAM, and Impact of Long Term Reliability on End of Life Vccmin. Proc. IEEE Int. Reliability Physics Symp., p.1008-1013.

[17]Sakurai, T., Newton, A.R., 1990. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J. Sol.-State Circ., 25(2):584-594.

[18]Sakurai, T., Newton, A.R., 1991. A simple MOSFET model for circuit analysis. IEEE Trans. Electron Dev., 38(4):887-894.

[19]Schroder, D.K., Babcock, J.A., 2003. Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing. J. Appl. Phys., 94(1):1-8.

[20]Seevinck, E., List, F., Lohstroh, J., 1987. Static-noise margin analysis of MOS transistors. IEEE J. Sol.-State Circ., 22(5):748-754.

[21]Tsividis, Y., 2003. Operation and Modeling of the MOS Transistor. Oxford University Press, USA.

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