Full Text:
<3797>
CLC number: TN405
On-line Access: 2013-04-03
Received: 2012-10-18
Revision Accepted: 2013-01-14
Crosschecked: 2013-03-15
Cited: 1
Clicked: 7730
Electrical characterization of integrated passive devices using thin film technology for 3D integration
| |||||||||||||
Xin Sun, Yun-hui Zhu, Zhen-hua Liu, Qing-hu Cui, Sheng-lin Ma, Jing Chen, Min Miao, Yu-feng Jin. Electrical characterization of integrated passive devices using thin film technology for 3D integration[J]. Journal of Zhejiang University Science C, 2013, 14(4): 235-243.
@article{title="Electrical characterization of integrated passive devices using thin film technology for 3D integration",
author="Xin Sun, Yun-hui Zhu, Zhen-hua Liu, Qing-hu Cui, Sheng-lin Ma, Jing Chen, Min Miao, Yu-feng Jin",
journal="Journal of Zhejiang University Science C",
volume="14",
number="4",
pages="235-243",
year="2013",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C12MNT01"
}
%0 Journal Article
%T Electrical characterization of integrated passive devices using thin film technology for 3D integration
%A Xin Sun
%A Yun-hui Zhu
%A Zhen-hua Liu
%A Qing-hu Cui
%A Sheng-lin Ma
%A Jing Chen
%A Min Miao
%A Yu-feng Jin
%J Journal of Zhejiang University SCIENCE C
%V 14
%N 4
%P 235-243
%@ 1869-1951
%D 2013
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C12MNT01
TY - JOUR
T1 - Electrical characterization of integrated passive devices using thin film technology for 3D integration
A1 - Xin Sun
A1 - Yun-hui Zhu
A1 - Zhen-hua Liu
A1 - Qing-hu Cui
A1 - Sheng-lin Ma
A1 - Jing Chen
A1 - Min Miao
A1 - Yu-feng Jin
J0 - Journal of Zhejiang University Science C
VL - 14
IS - 4
SP - 235
EP - 243
%@ 1869-1951
Y1 - 2013
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C12MNT01
Abstract: With the development of 3D Integration technology, microsystems with vertical interconnects are attracting attention from researchers and industry applications. Basic elements of integrated passive devices (IPDs), including inductors, capacitors, and resistors, could dramatically save the footprint of the system, optimize the form factor, and improve the performance of radio frequency (RF) systems. In this paper, IPDs using thin film built-up technology are introduced, and the design and characterization of coplanar waveguides (CPWs), inductors, and capacitors are presented.
[1]Arcioni, P., Castello, R., de Astis, G., Sacchi, E., Svelto, F., 1998. Measurement and modeling of Si integrated inductors. IEEE Trans. Instrum. Meas., 47(5):1372-1378.
[2]Ashby, K.B., Koullias, I.A., Finley, W.C., Bastek, J.J., Moinian, S., 1996. High Q inductors for wireless applications in a complementary silicon bipolar process. IEEE J. Sol.-State Circ., 31(1):4-9.
[3]Baron, J., Garrou, P., Pizzagalli, A., 2012. Polymeric Materials for 3DIC & Wafer-Level Packaging Applications (Sample Presentation). Available form http://www.i-micronews.com [Accessed on July 31, 2012].
[4]Beyne, E., 2008. Solving Technical and Economical Barriers to the Adoption of Through-Si-Via 3D Integration Technologies. 10 th Electronics Packaging Technology Conf., p.29-34.
[5]Cui, Q., Sun, X., Zhu, Y., Ma, S., Chen, J., Miao, M., Jin, Y., 2011. Design and Optimization of Redistribution Layer (RDL) on TSV Interposer for High Frequency Applications. IEEE Int. Conf. on Electronic Packaging Technology & High Density Packaging, p.1-5.
[6]Eisenstadt, W.R., Eo, Y., 1992. S-parameter-based IC interconnect transmission line characterization. IEEE Trans. Compon. Hybr. Manuf. Technol., 15(4):483-490.
[7]Frickey, D.A., 1994. Conversions between S, Z, Y, H, ABCD, and T parameters which are valid for complex source and load impedances. IEEE Trans. Microw. Theory Techn., 42(2):205-211.
[8]Kim, H., Eo, Y., 2008. High-frequency-measurement-based circuit modeling and power/ground integrity evaluation of integrated circuit packages. IEEE Trans. Adv. Pack., 31(4):910-918.
[9]Leung, L.L.W., Hon, W.C, Chen, K.J., 2004. Low-loss coplanar waveguides interconnects on low-resistivity silicon substrate. IEEE Trans. Compon. Pack. Technol., 27(3):507-512.
[10]Liu, K., Frye, R., Hlaing, M., Lee, Y., Kim, H., Kim, G., Ahn, B., 2012. Investigation of Integrated Passive Device with Through-Silicon Via. IEEE 62nd Electronic Components and Technology Conf., p.1833-1839.
[11]Lu, J., 2009. 3-D hyperintegration and packaging technologies for micro-nano systems. Proc. IEEE, 97(1):18-30.
[12]Mi, X., Takahashi, T., Ueda, S., 2008. Integrated Passives on LTCC for Achieving Chip-Sized-Modules. 38th European Microwave Conf., p.607-610.
[13]Ramm, P., Klumpp, A., Weber, J., Lietaer, N., Taklo, M., de Raedt, W., Fritzsch, T., Couderc, P., 2010. 3D Integration Technology: Status and Application Development. Proc. ESSCIRC, p.9-16.
[14]Siew, G., Soh, S., Tee, T.Y., Chen, H., Kang, I.S., Kim, J.H., 2011. Electrical Simulation and Measurement of IPD with Multilayer Thin Film Technology for WLP. IEEE Int. Conf. on Electronic Packaging Technology & High Density Packaging, p.659-664.
[15]Sun, X., Ji, M., Ma, S., Zhu, Y., Kang, W., Miao, M., Jin, Y., 2010. Electrical Characterization of Sidewall Insulation Layer of TSV. 11th Int. Conf. on Electronic Packaging Technology & High Density Packaging, p.77-80.
[16]Töpper, M., Fischer, T., Baumgartner, T., Reichl, H., 2010. A Comparison of Thin Film Polymers for Wafer Level Packaging. 60th Electronic Components and Technology Conf., p.769-776.
[17]Yook, J., Kim, J.C., Park, S., Ryu, J., Park, J.C., 2012. High Density and Low-Cost Silicon Interposer Using Thin-film and Organic Lamination Processes. IEEE 62nd Electronic Components and Technology Conf., p.274-278.
[18]Zhan, C., Tzeng, P., Lau, J.H., Dai, M., Chien, H., Lee, C., Wu, S., Kao, K., Huang, S., Fan, C., et al., 2012. Assembly Process and Reliability Assessment of TSV/RDL/IPD Interposer with Multi-Chip-Stacking for 3D IC Integration SiP. IEEE 62nd Electronic Components and Technology Conf., p.548-554.
[19]Zinck, C., 2010. 3D Integration Infrastructure & Market Status. IEEE Int. 3D Systems Integration Conf., p.1-34.
Open peer comments: Debate/Discuss/Question/Opinion
<1>