Deep search:Searching for "VLSI architecture" in 'ABSTRACTGot 3 items.
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1Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder
Author(s):Wan-yi LI, Lu YU  Clicked:5995  Download:3521  Cited:0  <Full Text>
Journal of Zhejiang University Science A  2008 Vol.9 No.12 P.1638-1643  DOI:10.1631/jzus.A0820112
2Parallel processing architecture of H.264 adaptive deblocking filters
Author(s):Hu WEI, Tao LIN, Zheng-hui LIN  Clicked:6065  Download:3261  Cited:1  <Full Text>
Journal of Zhejiang University Science A  2009 Vol.10 No.8 P.1160-1168  DOI:10.1631/jzus.A0820502
3High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) dec...
Author(s):Kai Huang, De Ma, Rong-jie Yan, Ha...  Clicked:7800  Download:4689  Cited:1  <Full Text>
Journal of Zhejiang University Science C  2013 Vol.14 No.6 P.449-463  DOI:10.1631/jzus.C1200250
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