| index | Title |
| 1 | Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM s... Author(s):Shou-biao Tan, Wen-juan Lu, Chun-y... Clicked:9811 Download:5084 Cited:1 <Full Text> <PPT> 2670 Frontiers of Information Technology & Electronic Engineering 2015 Vol.16 No.8 P.700-706 DOI:10.1631/FITEE.1400439 |