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index	Title
1	Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM s... Author(s):Shou-biao Tan, Wen-juan Lu, Chun-y...  Clicked:7236  Download:2832  Cited:1  <Full Text>  <PPT> 1937 Frontiers of Information Technology & Electronic Engineering  2015 Vol.16 No.8 P.700-706  DOI:10.1631/FITEE.1400439

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