• Home
• Content
  • Current Issue of JZUS-A
  • Current Issue of JZUS-B
  • Current Issue of FITEE
  • Current Issue of BDM
  • Back Issue of JZUS-A
  • Back Issue of JZUS-B
  • Back Issue of FITEE
  • Back Issue of BDM
  • In Press of JZUS-A
  • In Press of JZUS-B
  • In Press of FITEE
  • In Press of BDM
  • Highlights archive of JZUS-A
  • Highlights archive of JZUS-B
  • Highlights archive of FITEE
• Submit/Guide
  • Preparing Manuscript
  • Online Submission
  • Revision&Acceptance
  • Download
• Reviewer
  • Int'l Reviewer
  • Guidelines
• Ed. Board
  • JZUS-A
  • JZUS-B
  • FITEE
  • BDM
• Service
  • Polishing
  • Crosscheck
  • Advertisement
  • Conf. info.
  • Subscription
• Top 10 Rank
  • Top 10 Cited
  • Top 10 Downloads
• About
  • Policy
  • Awards
  • Editor Papers
  • Events
  • E-linK
  • Thanks Card
  • Contacts
• Subscribe
  • Issue Subscription

index	Title
1	Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM s... Author(s):Shou-biao Tan, Wen-juan Lu, Chun-y...  Clicked:7224  Download:2823  Cited:1  <Full Text>  <PPT> 1933 Frontiers of Information Technology & Electronic Engineering  2015 Vol.16 No.8 P.700-706  DOI:10.1631/FITEE.1400439

Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - 2024 Journal of Zhejiang University-SCIENCE