Abstract: A multi-stage dual replica bit-line delay (MDRBD) technique is proposed for reducing access time by suppressing the sense-amplifier enable (SAE) timing variation of low voltage static random-access memory (SRAM) applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-line (RBL) capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology (Taiwan Semiconductor Manufacturing Company, Taiwan).

用于低电压下SRAM灵敏放大器工艺变化鲁棒性时序的多级双复制位线延迟技术

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