Abstract: Reversible logic has recently gained significant interest due to its inherent ability to reduce energy dissipation, which is the primary need for low-power digital circuits. One of the newest areas of relevant study is reversible logic, which has applications in many areas, including nanotechnology, DNA computing, quantum computing, fault tolerance, and low-power complementary metal-oxide-semiconductor (CMOS). An electrical circuit is classified as reversible if it has an equal number of inputs and outputs, and a one-to-one relationship. A reversible circuit is conservative if the EXOR of the inputs and the EXOR of the outputs are equivalent. In addition, quantum-dot cellular automata (QCA) is one of the state-of-the-art approaches that can be used as an alternative to traditional technologies. Hence, we propose an efficient conservative gate with low power demand and high speed in this paper. First, we present a reversible gate called ANG (Ahmadpour Navimipour Gate). Then, two non-resistant QCA ANG and reversible fault-tolerant ANG structures are implemented in QCA technology. The suggested reversible gate is realized through the Miller algorithm. Subsequently, reversible fault-tolerant ANG is implemented by the 2DW clocking scheme. Furthermore, the power consumption of the suggested ANG is assessed under different energy ranges (0.5Ek, 1.0Ek, and 1.5Ek). Simulations of the structures and analysis of their power consumption are performed using QCADesigner 2.0.03 and QCAPro software. The proposed gate shows great improvements compared to recent designs.

基于量子点元胞自动机的超高效可逆块的纳米设计

[1]Abedi D, Jaberipur G, Sangsefidi M, 2015. Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover. IEEE Trans Nanotechnol, 14(3):497-504.

[2]Ahmadpour SS, Mosleh M, 2020. A novel ultra‐dense and low‐power structure for fault‐tolerant three‐input majority gate in QCA technology. Concurr Comput Pract Exp, 32(5):e5548.

[3]Ahmadpour SS, Navimipour NJ, Mosleh M, et al., 2022. An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform. Nano Commun Netw, 34:100412.

[4]Bahar AN, Wahid KA, 2020. Design of QCA-serial parallel multiplier (QSPM) with energy dissipation analysis. IEEE Trans Circ Syst II Express Briefs, 67(10):1939-1943.

[5]Bennett CH, 1973. Logical reversibility of computation. IBM J Res Dev, 17(6):525-532.

[6]Bhanja S, Sarkar S, 2008. Thermal switching error versus delay tradeoffs in clocked QCA circuits. IEEE Trans Very Large Scale Integr Syst, 16(5):528-541.

[7]Campos CAT, Marciano AL, Neto OPV, et al., 2016. USE: a universal, scalable, and efficient clocking scheme for QCA. IEEE Trans Comput-Aided Des Integr Circ Syst, 35(3):513-517.

[8]Feynman RP, 1986. Quantum mechanical computers. Found Phys, 16(6):507-531.

[9]Fredkin E, Toffoli T, 1982. Conservative logic. Int J Theor Phys, 21(3-4):219-253.

[10]Gong X, Wang LX, Mou YY, et al., 2022. Improved four-channel PBTDPA control strategy using force feedback bilateral teleoperation system. Int J Contr Autom Syst, 20(3):1002-1017.

[11]Haghparast M, Navi K, 2008a. Design of a novel fault tolerant reversible full adder for nanotechnology based systems. World Appl Sci J, 3(1):114-118.

[12]Haghparast M, Navi K, 2008b. A novel fault tolerant reversible gate for nanotechnology based systems. Am J Appl Sci, 5(5):519-523.

[13]Kundu A, Das JC, De D, 2022. RSCV: reversible select, cross and variation architecture in quantum‐dot cellular automata. IET Quant Commun, 3(2):139-149.

[14]Landauer R, 1961. Irreversibility and heat generation in the computing process. IBM J Res Dev, 5(3):183-191.

[15]Liu KQ, Ke F, Huang X, et al., 2021. DeepBAN: a temporal convolution-based communication framework for dynamic WBANs. IEEE Trans Commun, 69(10):6675-6690.

[16]Miller DM, Maslov D, Dueck GW, 2003. A transformation based algorithm for reversible logic synthesis. Proc Design Automation Conf, p.318-323.

[17]Noorallahzadeh M, Mosleh M, 2019. Efficient designs of reversible latches with low quantum cost. IET Circ Dev Syst, 13(6):806-815.

[18]Noorallahzadeh M, Mosleh M, 2020. Parity-preserving reversible flip-flops with low quantum cost in nanoscale. J Supercomput, 76(3):2206-2238.‏

[19]Norouzi M, Heikalabad SR, Salimzadeh F, 2020. A reversible ALU using HNG and Ferdkin gates in QCA nanotechnology. Int J Circ Theory Appl, 48(8):1291-1303.

[20]Parhami B, 2006. Fault-tolerant reversible circuits. Proc 40^th Asilomar Conf on Signals Systems Computers, p.1726-1729.

[21]Pramanik AK, Bhowmik D, Pal J, et al., 2022. Towards the realization of regular clocking-based QCA circuits using genetic algorithm. Comput Electr Eng, 97:107640.

[22]Roohi A, Zand R, Angizi S, et al., 2018. A parity-preserving reversible QCA gate with self-checking cascadable resiliency. IEEE Trans Emerg Top Comput, 6(4):450-459.

[23]Roy R, Sarkar S, Dhar S, 2021. Design and testing of a reversible ALU by quantum cells automata electro-spin technology. J Supercomput, 77(12):13601-13628.

[24]Safaiezadeh B, Mahdipour E, Haghparast M, et al., 2022. Novel design and simulation of reversible ALU in quantum dot cellular automata. J Supercomput, 78(1):868-882.

[25]Taskin B, Hong B, 2008. Improving line-based QCA memory cell design through dual phase clocking. IEEE Trans Very Large Scale Integr Syst, 16(12):1648-1656.

[26]Vankamamidi V, Ottavi M, Lombardi F, 2008. Two-dimensional schemes for clocking/timing of QCA circuits. IEEE Trans Comput-Aided Des Integr Circ Syst, 27(1):34-44.

[27]Walus K, Dysart TJ, Jullien GA, et al., 2004. QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans Nanotechnol, 3(1):26-31.

[28]Wang JW, Tian JW, Zhang X, et al., 2022. Control of time delay force feedback teleoperation system with finite time convergence. Front Neurorobot, 16:877069.

[29]Wang Z, Ramamoorthy R, Xi XJ, et al., 2022. Synchronization of the neurons coupled with sequential developing electrical and chemical synapses. Math Biosci Eng, 19(2):1877-1890.