JZUS - Journal of Zhejiang University SCIENCE

Frontiers of Information Technology & Electronic Engineering

Accepted manuscript available online (unedited version)

SAPER-AI accelerator: systolic array based power-efficient reconfigurable AI accelerator

Author(s): Fahad bin MUSLIM^†^‡¹ , Kashif INAYAT^†², Muhammad zain SIDDIQI^†¹ , Safiullah KHAN³, Tayyeb MAHMOOD⁴ , Ihtesham ul ISLAM⁵
Affiliation(s): ¹Faculty of Computer Science and Engineering, GIK Institute 23460, Pakistan; more
Corresponding email(s): fahad.muslim@giki.edu.pk, kashif.inayat@bsc.es, zain.siddiqi@giki.edu.pk
Key Words: AI accelerators; ASIC design; Systolic arrays; Low power designs

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Fahad bin MUSLIM^†^‡¹ , Kashif INAYAT^†², Muhammad zain SIDDIQI^†¹ , Safiullah KHAN³,Tayyeb MAHMOOD⁴ , Ihtesham ul ISLAM⁵. SAPER-AI accelerator: systolic array based power-efficient reconfigurable AI accelerator[J]. Frontiers of Information Technology & Electronic Engineering,in press.https://doi.org/10.1631/FITEE.2400867

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author="Fahad bin MUSLIM^†^‡¹ , Kashif INAYAT^†², Muhammad zain SIDDIQI^†¹ , Safiullah KHAN³,Tayyeb MAHMOOD⁴ , Ihtesham ul ISLAM⁵",
journal="Frontiers of Information Technology & Electronic Engineering",
year="in press",
publisher="Zhejiang University Press & Springer",
doi="https://doi.org/10.1631/FITEE.2400867"
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Abstract
Chinese Summary
Academic Network
Reviewer Comment

Abstract: Deep learning (DL) accelerators are critical for handling the growing computational demands of modern neural networks. Systolic array (SA) based accelerators consist of a 2D mesh of processing elements (PE) working cooperatively to accelerate matrix multiplication, a fundamental operation in DL. The power efficiency of such accelerators is of primary importance especially considering the edge AI regime. This work presents the SAPER-AI accelerator, an SA accelerator with power intent specified via a unified power format representation in a simplified manner with negligible micro-architectural optimization effort. Our proposed accelerator switches off rows and columns of PEs in a coarse-grained manner, thus leading to SA micro-architecture complying with the varying computational requirements of modern DL workloads. Our analysis demonstrates enhanced power efficiency ranging between 11% and 25% for the best case 32×32 and 64×64 SA designs, respectively. Additionally, the power delay product (PDP) exhibited a progressive improvement of around 6% for larger SA sizes. Moreover, a performance comparison between the MobileNet and ResNet50 models indicated generally better SA performance for the ResNet50 workload. This is due to the more regular convolutions portrayed by ResNet50 that are more favored by SAs, with the performance gap widening as the SA size increases.

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