Abstract: Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability. In battery-restricted applications such as handheld electronics systems, low-power FPGAs are in great demand. Leakage power almost equals dynamic power in modern integrated circuit technologies, so the reduction of leakage power leads to significant energy savings. We propose a power-efficient architecture for static random access memory (SRAM) based FPGAs, in which two modes (active mode and sleep mode) are defined for each module. In sleep mode, ultra-low leakage power is consumed by the module. The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors. After producing the correct outputs, the module returns to sleep mode. The proposed circuit design reduces the leakage power consumption in both active and sleep modes. The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina (MCNC) benchmark circuits on FPGA-SPICE software. Simulation results show an approximately 95% reduction in leakage power consumption in sleep mode. Moreover, the total power consumption (leakage+dynamic power consumption) is reduced by more than 15% compared with that of the best previous design. The average area overhead (4.26%) is less than those of other power-gating designs.

在现场可编程门阵列中用于降低泄漏功率的动态电源门控

[1]Ahmed I, Zhao SZ, Trescases O, et al., 2018. Automatic application-specific calibration to enable dynamic voltage scaling in FPGAs. IEEE Trans Comput-Aided Des Integr Circ Syst, 37(12):3095-3108.

[2]Ahmed I, Shen JL, Betz V, 2020. Optimizing FPGA logic circuitry for variable voltage supplies. IEEE Trans Very Large Scale Integr Syst, 28(4):890-903.

[3]Ahmed R, Bsoul AAM, Wilton SJE, et al., 2014. High-level synthesis-based design methodology for dynamic power-gated FPGA. Proc 24^th Int Conf on Field Programmable Logic and Applications, p.1-4.

[4]Ahmed R, Wilton SJE, Hallschmid P, et al., 2015. Hierarchical dynamic power-gating in FPGAs. Proc 11^th Int Symp on Applied Reconfigurable Computing, p.27-38.

[5]Amara A, Amiel F, Ea T, 2006. FPGA vs. ASIC for low power applications. Microelectron J, 37(8):669-677.

[6]Anderson JH, Najm FN, 2006. Active leakage power optimization for FPGAs. IEEE Trans Comput-Aided Des Integr Circ Syst, 25(3):423-437.

[7]Anderson JH, Najm FN, 2009. Low-power programmable FPGA routing circuitry. IEEE Trans Very Large Scale Integr Syst, 17(8):1048-1060.

[8]Bsoul AAM, Wilton SJE, 2010. An FPGA architecture supporting dynamically controlled power gating. Int Conf on Field-Programmable Technology, p.1-8.

[9]Bsoul AAM, Wilton SJE, Tsoi KH, et al., 2016. An FPGA architecture and CAD flow supporting dynamically controlled power gating. IEEE Trans Very Large Scale Integr Syst, 24(1):178-191.

[10]Chen DM, Cong J, Dong C, et al., 2010. Technology mapping and clustering for FPGA architectures with dual supply voltages. IEEE Trans Comput-Aided Des Integr Circ Syst, 29(11):1709-1722.

[11]Chen WT, Li L, Lu P, et al., 2016. Design of FPGA's high-speed and low-power programmable interconnect. Proc 13^th IEEE Int Conf on Solid-State and Integrated Circuit Technology, p.707-709.

[12]Colleman S, Verhelst M, 2021. High-utilization, high-flexibility depth-first CNN coprocessor for image pixel processing on FPGA. IEEE Trans Very Large Scale Integr Syst, 29(3):461-471.

[13]Ebrahimi Z, Khaleghi B, Asadi H, 2017. PEAF: a power-efficient architecture for SRAM-based FPGAs using reconfigurable hard logic design in dark silicon era. IEEE Trans Comput, 66(6):982-995.

[14]Hassan H, Anis M, Elmasry M, 2008. Input vector reordering for leakage power reduction in FPGAs. IEEE Trans Comput-Aided Des Integr Circ Syst, 27(9):1555-1564.

[15]Herath K, Prakash A, Fahmy SA, et al., 2021. Power-efficient mapping of large applications on modern heterogeneous FPGAs. IEEE Trans Comput-Aided Des Integr Circ Syst, 40(12):2508-2521.

[16]Huda S, Anderson JH, 2017. Leveraging unused resources for energy optimization of FPGA interconnect. IEEE Trans Very Large Scale Integr Syst, 25(8):2307-2320.

[17]Ishihara S, Hariyama M, Kameyama M, 2011. A low-power FPGA based on autonomous fine-grain power gating. IEEE Trans Very Large Scale Integr Syst, 19(8):1394-1406.

[18]Jahanirad H, 2019. CC-SPRA: correlation coefficients approach for signal probability-based reliability analysis. IEEE Trans Very Large Scale Integr Syst, 27(4):927-939.

[19]Kaur I, Rohilla L, Nagpal A, et al., 2018. Different configuration of low-power memory design using capacitance scaling on 28-nm field-programmable gate array. In: Muttoo SK (Ed.), System and Architecture. Springer, Singapore, p.151-161.

[20]Khaleghi B, Asadi H, 2018. A resistive RAM-based FPGA architecture equipped with efficient programming circuitry. IEEE Trans Circ Syst I Regul Pap, 65(7):2196-2209.

[21]Kim S, Na S, Kong BY, et al., 2021. Real-time SSDLite object detection on FPGA. IEEE Trans Very Large Scale Integr Syst, 29(6):1192-1205.

[22]Koppa S, John E, 2018. Performance tradeoffs in the design of low-power SRAM arrays for implantable devices. J Low Power Electron, 14(1):18-27.

[23]Kumar A, Anis M, 2007. Dual-threshold CAD framework for subthreshold leakage power aware FPGAs. IEEE Trans Comput-Aided Des Integr Circ Syst, 26(1):53-66.

[24]Kuon I, Rose J, 2007. Measuring the gap between FPGAs and ASICs. IEEE Trans Comput-Aided Des Integr Circ Syst, 26(2):203-215.

[25]Li F, Lin Y, He L, 2004. Vdd programmability to reduce FPGA interconnect power. IEEE/ACM Int Conf on Computer Aided Design, p.760-765.

[26]Li F, Lin Y, He L, 2007. Field programmability of supply voltages for FPGA power reduction. IEEE Trans Comput-Aided Des Integr Circ Syst, 26(4):752-764.

[27]Li J, Chow P, Peng YX, et al., 2021. FPGA implementation of an improved OMP for compressive sensing reconstruction. IEEE Trans Very Large Scale Integr Syst, 29(2):‍259-272.

[28]Lin MJ, El Gamal A, 2009. A low-power field-programmable gate array routing fabric. IEEE Trans Very Large Scale Integr Syst, 17(10):1481-1494.

[29]Lin Y, He L, 2006. Dual-Vdd interconnect with chip-level time slack allocation for FPGA power reduction. IEEE Trans Comput-Aided Des Integr Circ Syst, 25(10):‍2023-2034.

[30]Luu J, Goeders J, Wainberg M, et al., 2014. VTR 7.0: next generation architecture and CAD system for FPGAs. ACM Trans Reconfig Technol Syst, 7(2):6.

[31]Ma YF, Cao Y, Vrudhula S, et al., 2018. Optimizing the convolution operation to accelerate deep neural networks on FPGA. IEEE Trans Very Large Scale Integr Syst, 26(7):1354-1367.

[32]Mitra J, Nayak TK, 2018. An FPGA-based phase measurement system. IEEE Trans Very Large Scale Integr Syst, 26(1):133-142.

[33]Nguyen DT, Nguyen TN, Kim H, et al., 2019. A high-throughput and power-efficient FPGA implementation of YOLO CNN for object detection. IEEE Trans Very Large Scale Integr Syst, 27(8):1861-1873.

[34]Nunez-Yanez JL, Hosseinabady M, Beldachi A, 2016. Energy optimization in commercial FPGAs with voltage, frequency and logic scaling. IEEE Trans Comput, 65(5):‍‍1484-1493.

[35]Qi H, Ayorinde O, Calhoun BH, 2017. An ultra-low-power FPGA for IoT applications. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf, p.1-3.

[36]Rahimi H, Jahanirad H, 2021. An evolutionary approach to implement logic circuits on three dimensional FPGAs. Expert Syst Appl, 174:114780.

[37]Ramesh NVK, Uday Kiran K, NKSVS Reshma, et al., 2021. An efficient way to optimize the FPGA routing architecture. Proc 6^th Int Conf on Communication and Electronics Systems, p.209-211.

[38]Ravishankar C, Anderson JH, Kennings A, 2012. FPGA power reduction by guarded evaluation considering logic architecture. IEEE Trans Comput-Aided Des Integr Circ Syst, 31(9):1305-1318.

[39]Savari MA, Jahanirad H, 2020. NN-SSTA: a deep neural network approach for statistical static timing analysis. Expert Syst Appl, 149:113309.

[40]Seifoori Z, Khaleghi B, Asadi H, 2017. A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era. Design, Automation & Test in Europe Conf & Exhibition, p.1342-1347.

[41]Seifoori Z, Asadi H, Stojilović M, 2019. A machine learning approach for power gating the FPGA routing network. Int Conf on Field-Programmable Technology, p.10-18.

[42]Seifoori Z, Asadi H, Stojilović M, 2021. Shrinking FPGA static power via machine learning-based power gating and enhanced routing. IEEE Access, 9:115599-115619.

[43]Seomun J, Shin Y, 2011. Design and optimization of power-gated circuits with autonomous data retention. IEEE Trans Very Large Scale Integr Syst, 19(2):227-236.

[44]Singh P, Reniwal BS, Vijayvargiya V, et al., 2018. Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. Integration, 62:1-13.

[45]Tan BL, Lee WK, Mok KM, et al., 2018. Clock gating implementation on commercial field programmable gate array (FPGA). Proc 4^th Int Conf on Electrical, Electronics and System Engineering, p.102-106.

[46]Tang XF, Giacomin E, De Micheli G, et al., 2018. Post-P&R performance and power analysis for RRAM-based FPGAs. IEEE J Emerg Sel Top Circ Syst, 8(3):639-650.

[47]Tang XF, Giacomin E, De Micheli G, et al., 2019. FPGA-SPICE: a simulation-based architecture evaluation framework for FPGAs. IEEE Trans Very Large Scale Integr Syst, 27(3):637-650.

[48]Tatsumura K, Yazdanshenas S, Betz V, 2018. Enhancing FPGAs with magnetic tunnel junction‍-based block RAMs. ACM Trans Reconfig Technol Syst, 11(1):6.

[49]Tuan T, Rahman A, Das S, et al., 2007. A 90-nm low-power FPGA for battery-powered applications. IEEE Trans Comput-Aided Des Integr Circ Syst, 26(2):296-300.

[50]Vo MH, 2018. The merged clock gating architecture for low power digital clock application on FPGA. Int Conf on Advanced Technologies for Communications, p.282-286.

[51]Wagle A, Vrudhula S, 2022. Heterogeneous FPGA architecture using threshold logic gates for improved area, power, and performance. IEEE Trans Comput-Aided Des Integr Circ Syst, 41(6):1855-1867.

[52]Zhu JF, Pan LY, Yan YR, et al., 2014. A fast application-based supply voltage optimization method for dual voltage FPGA. IEEE Trans Very Large Scale Integr Syst, 22(12):‍2629-2634.