Abstract: Field Programmable Gate Array (FPGA) devices have become widespread in electronic systems due to their low design costs and their reconfigurability. In battery-restricted applications such as in handheld electronics systems, low-power FPGAs would be in great demand. The leakage power almost equals dynamic power in modern integrated circuit technologies, and so the reduction of leakage power leads to significant energy savings. This paper proposes a power-efficient architecture for SRAM-based FPGAs in which two modes (an active mode and a sleep mode) are defined for every module. In sleep mode, ultra-low leakage power is consumed by the module. The module mode changes from sleep mode to active mode dynamically when module outputs evaluate for new input vectors. After producing the correct outputs, the module goes back to sleep mode. The proposed circuit design reduces the leakage power consumption in both the active and sleep modes. The proposed low-leakage FPGA architecture is compared to the other state–of–the–art architectures by implementing MCNC benchmark circuits on FPGA-SPICE software. The simulation results show an approximately 95% reduction in leakage power consumption in sleep mode. Moreover, the total power consumption (leakage + dynamic power consumption) is reduced by more than 15% compared with the best previous design. The average area overhead (4.26%) is less than that of other power-gating designs.