Full Text:  <218>

Suppl. Mater.: 

CLC number: 

On-line Access: 2022-10-31

Received: 2022-03-05

Revision Accepted: 2022-10-10

Crosschecked: 0000-00-00

Cited: 0

Clicked: 122

Citations:  Bibtex RefMan EndNote GB/T7714

-   Go to

Article info.
Open peer comments

Frontiers of Information Technology & Electronic Engineering 

Accepted manuscript available online (unedited version)

Dynamic power-gating for leakage power reduction in FPGAs

Author(s):  Hadi JAHANIRAD

Affiliation(s):  Department of Electronics and Communication Engineering, University of Kurdistan, Sanandaj 66177-15175, Iran

Corresponding email(s):  h.jahanirad@uok.ac.ir

Key Words:  FPGA; Leakage power; Power-gating; Transistor-level circuit design

Share this article to: More <<< Previous Paper|Next Paper >>>

Hadi JAHANIRAD. Dynamic power-gating for leakage power reduction in FPGAs[J]. Frontiers of Information Technology & Electronic Engineering , 1998, -1(17): .

@article{title="Dynamic power-gating for leakage power reduction in FPGAs",
author="Hadi JAHANIRAD",
journal="Frontiers of Information Technology & Electronic Engineering",
publisher="Zhejiang University Press & Springer",

%0 Journal Article
%T Dynamic power-gating for leakage power reduction in FPGAs
%J Frontiers of Information Technology & Electronic Engineering
%V -1
%N -1
%@ 1869-1951
%D 1998
%I Zhejiang University Press & Springer

T1 - Dynamic power-gating for leakage power reduction in FPGAs
J0 - Frontiers of Information Technology & Electronic Engineering
VL - -1
IS - -1
SP -
EP -
%@ 1869-1951
Y1 - 1998
PB - Zhejiang University Press & Springer
ER -

Field Programmable Gate Array (FPGA) devices have become widespread in electronic systems due to their low design costs and their reconfigurability. In battery-restricted applications such as in handheld electronics systems, low-power FPGAs would be in great demand. The leakage power almost equals dynamic power in modern integrated circuit technologies, and so the reduction of leakage power leads to significant energy savings. This paper proposes a power-efficient architecture for SRAM-based FPGAs in which two modes (an active mode and a sleep mode) are defined for every module. In sleep mode, ultra-low leakage power is consumed by the module. The module mode changes from sleep mode to active mode dynamically when module outputs evaluate for new input vectors. After producing the correct outputs, the module goes back to sleep mode. The proposed circuit design reduces the leakage power consumption in both the active and sleep modes. The proposed low-leakage FPGA architecture is compared to the other state–of–the–art architectures by implementing MCNC benchmark circuits on FPGA-SPICE software. The simulation results show an approximately 95% reduction in leakage power consumption in sleep mode. Moreover, the total power consumption (leakage + dynamic power consumption) is reduced by more than 15% compared with the best previous design. The average area overhead (4.26%) is less than that of other power-gating designs.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


Open peer comments: Debate/Discuss/Question/Opinion


Please provide your name, email address and a comment

Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - 2023 Journal of Zhejiang University-SCIENCE