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CLC number: TN43
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2015-07-20
Cited: 1
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Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
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Shou-biao Tan, Wen-juan Lu, Chun-yu Peng, Zheng-ping Li, You-wu Tao, Jun-ning Chen. Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier[J]. Frontiers of Information Technology & Electronic Engineering, 2015, 16(8): 700-706.
@article{title="Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier",
author="Shou-biao Tan, Wen-juan Lu, Chun-yu Peng, Zheng-ping Li, You-wu Tao, Jun-ning Chen",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="16",
number="8",
pages="700-706",
year="2015",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1400439"
}
%0 Journal Article
%T Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
%A Shou-biao Tan
%A Wen-juan Lu
%A Chun-yu Peng
%A Zheng-ping Li
%A You-wu Tao
%A Jun-ning Chen
%J Frontiers of Information Technology & Electronic Engineering
%V 16
%N 8
%P 700-706
%@ 2095-9184
%D 2015
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1400439
TY - JOUR
T1 - Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
A1 - Shou-biao Tan
A1 - Wen-juan Lu
A1 - Chun-yu Peng
A1 - Zheng-ping Li
A1 - You-wu Tao
A1 - Jun-ning Chen
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 16
IS - 8
SP - 700
EP - 706
%@ 2095-9184
Y1 - 2015
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1400439
Abstract: A multi-stage dual replica bit-line delay (MDRBD) technique is proposed for reducing access time by suppressing the sense-amplifier enable (SAE) timing variation of low voltage static random-access memory (SRAM) applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-line (RBL) capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology (Taiwan Semiconductor Manufacturing Company, Taiwan).
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