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CLC number: TN47

On-line Access: 2024-08-27

Received: 2023-10-17

Revision Accepted: 2024-05-08

Crosschecked: 2009-10-18

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Journal of Zhejiang University SCIENCE A 2009 Vol.10 No.12 P.1801-1814

http://doi.org/10.1631/jzus.A0820853


Reliability assessment of networks-on-chip based on analytical models


Author(s):  Mojtaba VALINATAJ, Siamak MOHAMMADI, Saeed SAFARI

Affiliation(s):  School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran 14395-515, Iran

Corresponding email(s):   m.valinataj@ece.ut.ac.ir

Key Words:  Networks-on-chip (NoCs), Traffic model, Routing algorithm, Reliability assessment, Permanent fault


Mojtaba VALINATAJ, Siamak MOHAMMADI, Saeed SAFARI. Reliability assessment of networks-on-chip based on analytical models[J]. Journal of Zhejiang University Science A, 2009, 10(12): 1801-1814.

@article{title="Reliability assessment of networks-on-chip based on analytical models",
author="Mojtaba VALINATAJ, Siamak MOHAMMADI, Saeed SAFARI",
journal="Journal of Zhejiang University Science A",
volume="10",
number="12",
pages="1801-1814",
year="2009",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.A0820853"
}

%0 Journal Article
%T Reliability assessment of networks-on-chip based on analytical models
%A Mojtaba VALINATAJ
%A Siamak MOHAMMADI
%A Saeed SAFARI
%J Journal of Zhejiang University SCIENCE A
%V 10
%N 12
%P 1801-1814
%@ 1673-565X
%D 2009
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A0820853

TY - JOUR
T1 - Reliability assessment of networks-on-chip based on analytical models
A1 - Mojtaba VALINATAJ
A1 - Siamak MOHAMMADI
A1 - Saeed SAFARI
J0 - Journal of Zhejiang University Science A
VL - 10
IS - 12
SP - 1801
EP - 1814
%@ 1673-565X
Y1 - 2009
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.A0820853


Abstract: 
As technology scales down, the reliability issues are becoming more crucial, especially for networks-on-chip (NoCs) that provide the communication requirements of multi-processor systems-on-chip. Reliability evaluation based on analytical models is a precise method for dependability analysis before and after designing the fault-tolerant systems. In this paper, we accurately formulate the inherent reliability and vulnerability of some popular NoC architectures against permanent faults, also depending on the employed routing algorithm and traffic model. Based on this analysis, effects of failures in the links, switches and network interfaces on the packet delivery of NoCs are determined. Besides, some extensions to evaluate a fault-tolerant method and some routing algorithms are described. The analyses are validated through appropriate simulations. The results thus obtained are exactly the same as or very close to the analytical ones.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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