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Abstract: A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.

This manuscript describes a dual-edge implicit pulsed-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS), which employs the transmission-gatelogic-based (TGL) clock gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data keeps unchanged, so the redundant transitions of internal nodes are eliminated and the total power consumption is reduced. This paper has importance in VLSI design particularly in low power application.

采用内嵌时钟控制技术的低功耗双边沿隐形脉冲触发器

[1]Geng, L., Shen, J.Z., Xu, C.Y., 2016. Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications. IET Comput. Dig. Techn., 10(4):193-201.

[2]Goh, W.L., Yeo, K.S., Zhang, W., et al., 2007. A novel static dual edge-trigger flip-flop for high-frequency low-power application. IEEE Int. Symp. on Integrated Circuits, p.208-211.

[3]Hwang, Y.T., Lin, J.F., Sheu, M.H., 2012. Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme. IEEE Trans. VLSI Syst., 20(2):361-366.

[4]Hyman, R., Ranganathan, N., Bingel, T., et al., 2013. A clock control strategy for peak power and RMS current reduction using path clustering. IEEE Trans. VLSI Syst., 21(2):259-269.

[5]Judy, D.J., Kanchana Bhaaskaran, V.S., 2012. Energy recovery clock-gating scheme and negative edge triggering flip-flop for low power applications. Int. Conf. on Devices, Circuits and Systems, p.140-143.

[6]Kawaguchi, H., Takayasu, S., 1998. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J. Sol.-State Circuit., 33(5):807-811.

[7]Kim, S., Han, I., Paik, S., et al., 2011. Pulser gating: a clock-gating of pulsed-latch circuits. Proc. IEEE Asia South Pacific Design Automation Conf., p.190-195.

[8]Klass, F., Amir, C., Das, A., et al., 1999. A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. IEEE J. Sol.-State Circuit., 34(5):712-716.

[9]Ko, U., Balsara, P.T., 2000. High-performance energy-efficient D-flip-flop circuits. IEEE Trans. VLSI Syst., 8(1):94-98.

[10]Kong, B.S., Kim, S.S., Jun, Y.H., 2001. Conditional-capture flip-flop for statistical power reduction. IEEE J. Solid-State Circuits, 36(8):1263-1271.

[11]Kulkarni, S.H., Sylvester, D., 2004. High performance level conversion for dual V_DD design. IEEE Trans. VLSI Syst., 12(9):926-936.

[12]Maxim, A., Gheorghe, M., 2001. A novel physical based model of deep submicron CMOS transistors mismatch for Monte Carlo SPICE simulation. IEEE Int. Symp. on Circuits and Systems, p.511-514.

[13]Nedovic, N., Aleksic, M., Oklobdzija, V.G., 2002. Conditional pre-charge techniques for power-efficient dual-edge clocking. Proc. Int. Symp. on Low Power Electronics and Design, p.56-59.

[14]Phyu, M.W., Fu, K., Goh, W.L., et al., 2011. Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. IEEE Trans. VLSI Syst., 19(1):1-9.

[15]Shen, J.Z., Geng, L., Wu, X.X., 2015. Low power pulse-triggered flip-flop based on clock triggering edge control technique. J. Circuit. Syst. Comput., 24(07):1550094.

[16]Stojanovic, V., Oklobdzija, V.G., 1999. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE J. Sol.-State Circuit., 34(4):536-548.

[17]Strollo, A.G.M., de Caro, D., Napoli, E., et al., 2005. A novel high-speed sense-amplifier-based flip-flop. IEEE Trans. VLSI Syst., 13(11):1266-1274.

[18]Teh, C.K., Hamada, M., Fujita, T., et al., 2006. Conditional data mapping flip-flops for low-power and high-performance systems. IEEE Trans. VLSI Syst., 14(12):1379-1383.

[19]Teh, C.K., Fujita, T., Hara, H., et al., 2011. A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adoptive-coupling configuration in 40nm CMOS. Proc. IEEE Int. Sol.-State Circuit. Conf. on Digest of Technical Papers, p.338-340.

[20]Weste, N.H.E., 2006. CMOS VLSI Design: a Circuits and Systems Perspective (3rd Ed.). Pearson Education, Noida, India.

[21]Wu, Q., Pedram, M., Wu, X., 2000. Clock-gating and its application to low power design of sequential circuits. IEEE Trans. Circuit Syst.-I, 47(3):415-420.

[22]Wu, X.X., Shen, J.Z., 2012. Low-power explicit-pulsed triggered flip-flop with robust output. Electron. Lett., 48(24):1523-1525.

[23]Xiang, G.P., Shen, J.Z., Wu, X.X., et al., 2013. Design of a low-power pulse-triggered flip-flop with conditional clock technique. IEEE Int. Symp. on Circuits and Systems, p.121-124.

[24]Zeitzoff, P.M., Chung, J.E., 2005. A perspective from the 2003 ITRS: MOSFET scaling trends, challenges, and potential solutions. IEEE Circuit. Devic. Mag., 21(1):4-15.

[25]Zhao, P., Darwish, T.K., Bayoumi, M.A., 2004. High-performance and low power conditional discharge flip-flop. IEEE Trans. VLSI Syst., 12(5):477-484.