JZUS - Journal of Zhejiang University SCIENCE

Frontiers of Information Technology & Electronic Engineering 2016 Vol.17 No.11 P.1228-1244

A modified simulated annealing algorithm and an excessive area model for floorplanning using fixed-outline constraints

Author(s): De-xuan Zou, Gai-ge Wang, Gai Pan, Hong-wei Qi
Affiliation(s): School of Electrical Engineering and Automation, Jiangsu Normal University, Xuzhou 221116, China; more
Corresponding email(s): zoudexuan@163.com
Key Words: Fixed-outline floorplanning, Modified simulated annealing algorithm, Global search, Excessive area model, B*-tree representation

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Abstract: Outline-free floorplanning focuses on area and wirelength reductions, which are usually meaningless, since they can hardly satisfy modern design requirements. We concentrate on a more difficult and useful issue, fixed-outline floorplanning. This issue imposes fixed-outline constraints on the outline-free floorplanning, making the physical design more interesting and challenging. The contributions of this paper are primarily twofold. First, a modified simulated annealing (MSA) algorithm is proposed. In the beginning of the evolutionary process, a new attenuation formula is used to decrease the temperature slowly, to enhance MSA’s global searching capacity. After a period of time, the traditional attenuation formula is employed to decrease the temperature rapidly, to maintain MSA’s local searching capacity. Second, an excessive area model is designed to guide MSA to find feasible solutions readily. This can save much time for refining feasible solutions. Additionally, b*-tree representation is known as a very useful method for characterizing floorplanning. Therefore, it is employed to perform a perturbing operation for MSA. Finally, six groups of benchmark instances with different dead spaces and aspect ratios—circuits n10, n30, n50, n100, n200, and n300—are chosen to demonstrate the efficiency of our proposed method on fixed-outline floorplanning. Compared to several existing methods, the proposed method is more efficient in obtaining desirable objective function values associated with the chip area, wirelength, and fixed-outline constraints.

In this paper, a simulated annealing algorithm and excessive area model are developed for the floorplanning problem. The literature review and problem statement are acceptable. The paper is organized in an understandable manner. Simulated annealing process is one of the many other heuristics methods and the authors propose the SA modification as the originality of the work. Excessive area model is also included. They have used six combinations to evaluate the performance of the proposed approaches. They have choosen the methods that returned best results for each combination.

基于修正模拟退火算法及溢出面积模型的固定边界布图规划

概要：无边界布图规划研究面积及线长减少问题很难满足现代设计需求，因此通常被认为是无意义的。我们关注一种难度更大且更有意义的问题--固定边界布图规划。该问题将固定边界约束条件加入无边界布图规划中，使其在实体设计中更有趣、更具挑战性。本文的工作主要分为两部分。第一，提出了一种修正模拟退火算法（Modified simulated annealing algorithm, MSA）。在进化过程初期，用一种新的衰减方程来缓慢减小温度，以增强MSA的全局搜索能力。然后，用传统衰减方程来快速减小温度，以维持MSA的局部搜索能力。第二，设计了一种溢出面积模型来引导MSA寻找可行解，为精炼可行解节省了大量时间。另外，B*-tree是一种有效的布图规划表示法，它被用来执行MSA的扰动操作。最后，以六组带有不同空置率及高宽比的benchmark为例，证实本文所提方法在解决固定边界布图规划问题上的效率，这些问题包括电路n10，n30，n50，n100，n200和n300。与几种现有方法相比，本方法能够更有效地获得令人满意的目标函数值，它们与芯片面积、线长和固定边界约束有关。

关键词：固定边界布图规划；修正的模拟退火算法；全局搜索；溢出面积模型；B*-tree表示法

Reference

[1]Adya, S.N., Markov, I.L., 2003. Fixed-outline floorplanning: enabling hierarchical design. IEEE Trans. VLSI Syst., 11(6):1120-1135.

[2]Chambari, A., Najafi, A.A., Rahmati, S.H.A., et al., 2013. An efficient simulated annealing algorithm for the redundancy allocation problem with a choice of redundancy strategies. Reliab. Eng. Syst. Safety, 119:158-164.

[3]Chang, Y.C., Chang, Y.W., Wu, G.M., et al., 2000. B*-trees: a new representation for non-slicing floorplans. Proc. Design Automation Conf., p.458-463.

[4]Chen, S., Yoshimura, T., 2008. Fixed-outline floorplanning: block-position enumeration and a new method for calculating area costs. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 27(5):858-871.

[5]Chen, T.C., Chang, Y.W., 2006. Modern floorplanning based on B*-tree and fast simulated annealing. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 25(4):637-650.

[6]Chen, T.C., Chang, Y.W., Lin, S.C., 2008. A new multilevel framework for large-scale interconnect-driven floorplanning. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 27(2):286-294.

[7]Cong, J., Wei, J., Zhang, Y., 2004. A thermal-driven floorplanning algorithm for 3D ICs. IEEE/ACM Int. Conf. on Computer Aided Design, p.306-313.

[8]Goodson, J.C., 2015. A priori policy evaluation and cyclic-order-based simulated annealing for the multi-compartment vehicle routing problem with stochastic demands. Eur. J. Oper. Res., 241(2):361-369.

[9]Guo, P.N., Cheng, C.K., Yoshimura, T., 1999. An O-tree representation of non-slicing floorplans and its applications. Proc. Design Automation Conf., p.268-273.

[10]Haridass, K., Valenzuela, J., Yucekaya, A.D., et al., 2014. Scheduling a log transport system using simulated annealing. Inform. Sci., 264:302-316.

[11]Heller, W.R., Maling, K., Sorkin, G., 1982. The planar package for system designers. Proc. Design Automation Conf., p.253-260.

[12]Hoo, C.S., Kanesan, J., Ramiah, H., 2014. Enumeration technique in very large-scale integration fixed-outline floorplanning. IET Circ. Dev. Syst., 8(1):47-57.

[13]Kahng, A.B., 2000. Classical floorplanning harmful Proc. Int. Symp. on Physical Design, p.207-213.

[14]Kahng, A.B., Markov, I., 2007. GSRC Floorplan Benchmark. Available from http://vlsicad.eecs.umich.edu/BK/ GSRCbench/HARD/.

[15]Kennedy, J., Eberhart, R.C., 1995. Particle swarm optimization. Proc. IEEE Int. Conf. on Neural Networks, p.1942-1948.

[16]Khan, A.K., Vatsa, R., Roy, S., et al., 2014. A new efficient topological structure for floorplanning in 3D VLSI physical design. IEEE Int. Advance Computing Conf., p.696-701.

[17]Kirpatrick, S., Gelatt, C.D., Vecchi, M.P., 1983. Optimization by simulated annealing. Science, 220(4598):671-680.

[18]Lin, J.M., Chang, Y.W., 2001. TCG: a transitive closure graph-based representation for non-slicing floorplans. Proc. Design Automation Conf., p.764-769.

[19]Lin, J.M., Hung, Z.X., 2012. SKB-tree: a fixed-outline driven representation for modern floorplanning problems. IEEE Trans. VLSI Syst., 20(3):473-484.

[20]Lin, S.W., Yu, V.F., 2015. A simulated annealing heuristic for the multiconstraint team orienteering problem with multiple time windows. Appl. Soft Comput., 37:632-642.

[21]Liu, R., Dong, S., Hong, X., et al., 2005. Fixed-outline floorplanning with constraints through instance augmentation. IEEE Int. Symp. on Circuits and Systems, p.1883-1886.

[22]Ma, T.L., Young, E.F.Y., 2008. TCG-based multi-bend bus driven floorplanning. Design Automation Conf., p.192-197.

[23]Maling, K., Heller, W.R., Mueller, S.H., 1982. On finding most optimal rectangular package plans. Proc. Design Automation Conf., p.663-670.

[24]Murata, H., Fujiyoshi, K., Nakatake, S., et al., 1996. VLSI module placement based on rectangle-packing by the sequence pair. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 15(12):1518-1524.

[25]Otten, R.H.J.M., 1982. Automatic floorplan design. Proc. Design Automation Conf., p.261-267.

[26]Storn, R., Price, K., 1997. Differential evolution—a simple and efficient heuristic for global optimization over continuous spaces. J. Glob. Optim., 11(4):341-359.

[27]Wang, S.L., Zuo, X.Q., Liu, X.Q., et al., 2015. Solving dynamic double row layout problem via combining simulated annealing and mathematical programming. Appl. Soft Comput., 37:303-310.

[28]Wong, D.F., Liu, C.L., 1986. A new algorithm for floorplan design. Proc. Design Automation Conf., p.101-107.

[29]Wong, K.W.C., Young, E.F.Y., 2003. Fast buffer planning and congestion optimization in interconnect-driven floorplanning. Proc. Design Automation Conf., p.411-416.

[30]Wu, P.H., Ho, T.Y., 2011. Thermal-aware bus-driven floorplanning. Int. Symp. on Low Power Electronics and Design, p.205-210.

[31]h ttp://dx.doi.org/10.1109/ISLPED.2011.5993637

[32]Xiang, H., Tang, X.P., Wong, M.D.F., 2004. Bus-driven floorplanning. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 23(11):1522-1530.

[33]Yan, J.T., 2006. Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning. IEEE Proc. on Computers and Digital Techniques, p.335-347.

[34]Yan, J.Z., Chu, C., 2010. DeFer: deferred decision making enabled fixed-outline floorplanning algorithm. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 29(3):367-381.

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