CLC number: TP302
On-line Access: 2024-11-08
Received: 2023-07-08
Revision Accepted: 2024-11-08
Crosschecked: 2023-12-19
Cited: 0
Clicked: 757
Chenglong SUN, Yiming OUYANG, Huaguo LIANG. Traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing[J]. Frontiers of Information Technology & Electronic Engineering, 2024, 25(10): 1322-1336.
@article{title="Traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing",
author="Chenglong SUN, Yiming OUYANG, Huaguo LIANG",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="25",
number="10",
pages="1322-1336",
year="2024",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2300458"
}
%0 Journal Article
%T Traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing
%A Chenglong SUN
%A Yiming OUYANG
%A Huaguo LIANG
%J Frontiers of Information Technology & Electronic Engineering
%V 25
%N 10
%P 1322-1336
%@ 2095-9184
%D 2024
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2300458
TY - JOUR
T1 - Traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing
A1 - Chenglong SUN
A1 - Yiming OUYANG
A1 - Huaguo LIANG
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 25
IS - 10
SP - 1322
EP - 1336
%@ 2095-9184
Y1 - 2024
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2300458
Abstract: As the number of cores in a multicore system increases, the communication pressure on the interconnection network also increases. The network-on-chip (NoC) architecture is expected to take on the ever-expanding communication demands triggered by the ever-increasing number of cores. The communication behavior of the NoC architecture exhibits significant spatial–temporal variation, posing a considerable challenge for NoC reconfiguration. In this paper, we propose a traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing to adapt to the varying traffic flows with a high flexibility. First, a modified input port is introduced to support buffer sharing between adjacent ports. Specifically, the modified input port can be dynamically reconfigured to react to on-demand traffic. Second, it is ascertained that a centralized output-oriented buffer management works well with the reconfigurable input ports. Finally, this reconfiguration method can be implemented with a low overhead hardware design without imposing a great burden on the system implementation. The experimental results show that compared to other proposals, the proposed NoC architecture can greatly reduce the packet latency and improve the saturation throughput, without incurring significant area and power overhead.
[1]Baharloo M, Khonsari A, 2018. A low-power wireless-assisted multiple network-on-chip. Microprocess Microsyst, 63:104-115.
[2]Castillo EV, Miorandi G, Chau WJ, 2014. DyAFNoC: characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithm. Proc 8th IEEE/ACM Int Symp on Networks-on-Chip, p.190-191.
[3]Catania V, Mineo A, Monteleone S, et al., 2017. Cycle-accurate network on chip simulation with Noxim. ACM Trans Model Comput Simul, 27(1):4.
[4]Chen XN, Peh LS, 2003. Leakage power modeling and optimization in interconnection networks. Proc Int Symp on Low Power Electronics and Design, p.90-95.
[5]Das TS, Ghosal P, Chatterjee N, 2021. VCS: a method of in-order packet delivery for adaptive NoC routing. Nano Commun Netw, 28:100333.
[6]Farrokhbakht H, Kao H, Jerger NE, 2019. UBERNoC: unified buffer power-efficient router for network-on-chip. Proc 13th IEEE/ACM Int Symp on Networks-on-Chip, p.1-8.
[7]Jain A, Laxmi V, Tripathi M, et al., 2020. TRACK: an algorithm for fault-tolerant, dynamic and scalable 2D mesh network-on-chip routing reconfiguration. Integration, 72:92-110.
[8]Jerger NE, Krishna T, Peh LS, 2017. On-Chip Networks (2nd Ed.). Springer, Cham, Germany.
[9]Jindal N, Gupta S, Ravipati DP, et al., 2020. Enhancing network-on-chip performance by reusing trace buffers. IEEE Trans Comput-Aided Des Integr Circ Syst, 39(4):922-935.
[10]Krishna T, Chen CHO, Kwon WC, et al., 2013a. Breaking the on-chip latency barrier using SMART. Proc IEEE 19th Int Symp on High Performance Computer Architecture, p.378-389.
[11]Krishna T, Chen CHO, Park S, et al., 2013b. Single-cycle multihop asynchronous repeated traversal: a smart future for reconfigurable on-chip networks. Computer, 46(10):48-55.
[12]Kumar A, Peh LS, Kundu P, et al., 2007. Express virtual channels: towards the ideal interconnection fabric. ACM SIGARCH Comput Archit News, 35(2):150-161.
[13]Kumar S, Jantsch A, Soininen JP, et al., 2002. A network on chip architecture and design methodology. Proc IEEE Computer Society Annual Symp on VLSI. New Paradigms for VLSI Systems Design, p.117-124.
[14]Lan YC, Lin HA, Lo SH, et al., 2011. A bidirectional NoC (BiNoC) architecture with dynamic self-reconfigurable channel. IEEE Trans Comput-Aided Des Integr Circ Syst, 30(3):427-440.
[15]Li J, Qin CQ, Sun XC, 2023. An efficient adaptive routing algorithm for the co-optimization of fault tolerance and congestion awareness based on 3D NoC. Microelectron J, 142:105989.
[16]Matos D, Concatto C, Kreutz M, et al., 2011. Reconfigurable routers for low power and high performance. IEEE Trans Very Large Scale Integr (VLSI) Syst, 19(11):2045-2057.
[17]Nguyen HK, Tran XT, 2019. A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs. J Syst Archit, 100:101664.
[18]Nicopoulos CA, Park D, Kim J, et al., 2006. ViChaR: a dynamic virtual channel regulator for network-on-chip routers. Proc 39th Annual IEEE/ACM Int Symp on Microarchitecture, p.333-346.
[19]Ouyang YM, Sun CL, Jia BY, et al., 2021. Architecting a priority-based dynamic media access control mechanism in wireless network-on-chip. Microelectron J, 116:105218.
[20]Ouyang YM, Sun CL, Li RF, et al., 2023. Transit ring: bubble flow control for eliminating inter-ring communication congestion. J Supercomput, 79(2):1161-1181.
[21]Oveis-Gharan M, Khan GN, 2016. Efficient dynamic virtual channel organization and architecture for NoC systems. IEEE Trans Very Large Scale Integr (VLSI) Syst, 24(2):465-478.
[22]Oveis-Gharan M, Khan GN, 2020. Reconfigurable on-chip interconnection networks for high performance embedded SoC design. J Syst Archit, 106:101711.
[23]Qian ZL, Abbas SM, Tsui CY, 2015. FSNoC: a flit-level speedup scheme for network on-chips using self-reconfigurable bidirectional channels. IEEE Trans Very Large Scale Integr (VLSI) Syst, 23(9):1854-1867.
[24]Said M, Sarihi A, Patooghy A, et al., 2021. Novel flexible buffering architectures for 3D-NoCs. Sustain Comput Inform Syst, 29:100472.
[25]Seitanidis I, Psarras A, Chrysanthou K, et al., 2015. Elasti-Store: flexible elastic buffering for virtual-channel-based networks on chip. IEEE Trans Very Large Scale Integr (VLSI) Syst, 23(12):3015-3028.
[26]Stensgaard MB, Sparsø J, 2008. ReNoC: a network-on-chip architecture with reconfigurable topology. Proc 2nd ACM/IEEE Int Symp on Networks-on-Chip, p.55-64.
[27]Stuart MB, Stensgaard MB, Sparsø J, 2011. The ReNoC reconfigurable network-on-chip: architecture, configuration algorithms, and evaluation. ACM Trans Embed Comput Syst, 10(4):45.
[28]Wang HS, Peh LS, Malik S, 2003. Power-driven design of router microarchitectures in on-chip networks. Proc 36th Annual IEEE/ACM Int Symp on Microarchitecture, p.105-116.
[29]Wang L, Liu LB, Han J, et al., 2020. Achieving flexible global reconfiguration in NoCs using reconfigurable rings. IEEE Trans Parall Distrib Syst, 31(3):611-622.
[30]Wu YB, Liu LB, Wang L, et al., 2020. Aggressive fine-grained power gating of NoC buffers. IEEE Trans Comput-Aided Des Integr Circ Syst, 39(11):3177-3189.
[31]Ye TT, De Micheli G, Benini L, 2002. Analysis of power consumption on switch fabrics in network routers. Proc 39th Annual Design Automation Conf, p.524-529.
[32]Zheng H, Wang K, Louri A, 2021. Adapt-NoC: a flexible network-on-chip design for heterogeneous manycore architectures. Proc IEEE Int Symp on High-Performance Computer Architecture, p.723-735.
[33]Zoni D, Flich J, Fornaciari W, 2016. CUTBUF: buffer management and router design for traffic mixing in VNET-based NoCs. IEEE Trans Parall Distrib Syst, 27(6):1603-1616.
Open peer comments: Debate/Discuss/Question/Opinion
<1>