Full Text:   <1898>

Summary:  <741>

CLC number: TP309

On-line Access: 2021-11-15

Received: 2020-12-09

Revision Accepted: 2021-03-08

Crosschecked: 2021-10-12

Cited: 0

Clicked: 3353

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Lang Li

https://orcid.org/0000-0002-4832-4499

Jingya Feng

https://orcid.org/0000-0002-8109-1201

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Frontiers of Information Technology & Electronic Engineering  2021 Vol.22 No.11 P.1505-1516

http://doi.org/10.1631/FITEE.2000688


Implementation of PRINCE with resource-efficient structures based on FPGAs


Author(s):  Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li

Affiliation(s):  Hunan Provincial Key Laboratory of Intelligent Information Processing and Application, Hengyang Normal University, Hengyang 421002, China; more

Corresponding email(s):   lilang911@126.com, fengjyk@126.com

Key Words:  Lightweight block cipher, Field-programmable gate array (FPGA), Low-cost, PRINCE, Embedded security


Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li. Implementation of PRINCE with resource-efficient structures based on FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(11): 1505-1516.

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Abstract: 
In this era of pervasive computing, low-resource devices have been deployed in various fields. PRINCE is a lightweight block cipher designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for PRINCE components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components, we propose three new hardware architectures for PRINCE. The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, low-cost, and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The low-cost architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of PRINCE, the new low-cost architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight, latency-critical applications.

基于FPGA的资源节约型结构PRINCE的实现

李浪1,2,3,冯景亚1,2,刘波涛1,3,郭影1,3,李秋萍1,3
1衡阳师范学院智能信息处理与应用湖南省重点实验室,中国衡阳市,421002
2湖南师范大学信息科学与工程学院,中国长沙市,410081
3衡阳师范学院计算机科学与技术学院,中国衡阳市,421002
摘要:在当今普适计算时代,低资源设备已广泛部署在各个领域。PRINCE是一种专为低延迟设计的轻量级分组密码,适用于普适计算应用程序。本文通过共享和简化逻辑电路为PRINCE组件提出新的电路结构,以达到使用较少逻辑门获得相同效果的目标。基于组件新的电路结构和组件之间的最佳共享,提出3种新的PRINCE硬件架构,并在不同可编程门阵列设备上对3种硬件架构进行仿真和综合。基于Virtex-6平台的实验结果表明,与现有架构相比,展开、低成本和两周期架构的资源消耗分别减少73、119和380个可编程逻辑单元。低成本架构仅需137个可编程逻辑单元。展开架构需409个可编程逻辑单元,其吞吐量为5.34 Gb/s。据我们所知,对于PRINCE的硬件实现,所提低成本架构具有更低资源消耗,且所提展开架构具有更高吞吐量。因此,所提架构具有更高资源效率,适用于低资源、低延迟的应用程序。

关键词:轻量级分组密码;现场可编程门阵列(FPGA);低成本;PRINCE;嵌入式安全

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