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CLC number: TN79

On-line Access: 2023-05-06

Received: 2022-03-05

Revision Accepted: 2022-10-10

Crosschecked: 2023-05-06

Cited: 0

Clicked: 957

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Hadi JAHANIRAD

https://orcid.org/0000-0001-8586-6281

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Frontiers of Information Technology & Electronic Engineering  2023 Vol.24 No.4 P.582-598

http://doi.org/10.1631/FITEE.2200084


Dynamic power-gating for leakage power reduction in FPGAs


Author(s):  Hadi JAHANIRAD

Affiliation(s):  Department of Electronics and Communication Engineering, University of Kurdistan, Sanandaj 66177-15175, Iran

Corresponding email(s):   h.jahanirad@uok.ac.ir

Key Words:  Field programmable gate array (FPGA), Leakage power, Power-gating, Transistor-level circuit design


Hadi JAHANIRAD. Dynamic power-gating for leakage power reduction in FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(4): 582-598.

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Abstract: 
field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability. In battery-restricted applications such as handheld electronics systems, low-power FPGAs are in great demand. leakage power almost equals dynamic power in modern integrated circuit technologies, so the reduction of leakage power leads to significant energy savings. We propose a power-efficient architecture for static random access memory (SRAM) based FPGAs, in which two modes (active mode and sleep mode) are defined for each module. In sleep mode, ultra-low leakage power is consumed by the module. The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors. After producing the correct outputs, the module returns to sleep mode. The proposed circuit design reduces the leakage power consumption in both active and sleep modes. The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina (MCNC) benchmark circuits on FPGA-SPICE software. Simulation results show an approximately 95% reduction in leakage power consumption in sleep mode. Moreover, the total power consumption (leakage+dynamic power consumption) is reduced by more than 15% compared with that of the best previous design. The average area overhead (4.26%) is less than those of other power-gating designs.

在现场可编程门阵列中用于降低泄漏功率的动态电源门控

Hadi JAHANIRAD
库尔德斯坦大学电子与通信工程系,伊朗萨南达季市,66177-15175
摘要:现场可编程门阵列(FPGA)器件由于其低设计成本和可重构性,在电子系统中得到广泛应用。在手持电子系统等电池受限的应用中,低功耗FGPA的需求很大。在现代集成电路技术中,泄漏功率几乎相当于动态功率,因此降低泄漏功率可以显著节省能耗。我们提出一种基于静态随机存取存储器(SRAM)的FPGA高效架构,其中每个模块定义了两种模式(活动模式和休眠模式)。在休眠模式下,模块消耗超低泄漏功率。当模块输出对新输入向量的评估时,模块模式由休眠模式动态改变为活动模式。在产生正确的输出后,该模块返回到休眠模式。所提电路设计在活动模式和休眠模式下都降低了泄漏功耗。通过在FPGA-SPICE软件上实现北卡罗来纳州微电子中心(MCNC)基准电路,将所提出的低泄漏FPGA体系结构与最先进的体系结构进行比较。仿真结果表明,休眠模式下泄漏功耗降低约95%。此外,与以往的最佳设计相比,总功耗(泄漏功耗+动态功耗)降低15%以上。平均面积开销(4.26%)小于其他电源门控设计。

关键词:现场可编程门阵列(FPGA);泄漏功率;电源门控;晶体管级电路设计

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

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