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Journal of Zhejiang University SCIENCE C 1998 Vol.-1 No.-1 P.

http://doi.org/10.1631/FITEE.2300454


Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH


Author(s):  Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU

Affiliation(s):  China Electronics Technology Group Corporation No. 58 Research Institute, Wuxi 214035, China

Corresponding email(s):   caozhengzhou@163.com

Key Words:  FPGA, programmable logic element, Boolean logic operation, look-up table, Sense-Switch pFLASH, threshold voltage


Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU. Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH[J]. Frontiers of Information Technology & Electronic Engineering, 1998, -1(-1): .

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author="Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU",
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year="1998",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2300454"
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%T Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
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%A Guozhu LIU
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%J Journal of Zhejiang University SCIENCE C
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A1 - Yuting XU
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Abstract: 
This article proposes a kind of programmable logic element (PLE) based on sense-Switch pFLASH technology. By programming sense-Switch pFLASH, all 3-bit look-up table (LUT3) functions, partial LUT4 functions, latch functions, and DFF functions with enable and reset can be realized. Because the PLE uses a choice of operational logic (COOL) approach to the operation of logical functions, it allows any logic circuit to be implemented using any combinatorial logic and register ratio. This intrinsic property makes it close to the basic ASIC cell in terms of fine granularity, thus allowing ASIC-like cell-based mappers to apply all their optimization potential. By measuring sense-Switch pFLASH and PLE circuits, the results show that the "on" state driving current of the sense-Switch pFLASH is about 245.52 μA, and the "off" state leakage current is about 0.1 pA. The programmable function of PLE works normally. The delay of the typical combinatorial logic operation AND3 is 0.69 nS, and the delay of the sequential logic operation DFF is 0.65 nS, both of which meet the requirements of the design technical index.

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