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Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
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Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU. Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH[J]. Frontiers of Information Technology & Electronic Engineering, 1998, -1(-1): .
@article{title="Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH",
author="Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="-1",
number="-1",
pages="",
year="1998",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2300454"
}
%0 Journal Article
%T Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
%A Zhengzhou CAO
%A Guozhu LIU
%A Yanfei ZHANG
%A Yueer SHAN
%A Yuting XU
%J Journal of Zhejiang University SCIENCE C
%V -1
%N -1
%P
%@ 2095-9184
%D 1998
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2300454
TY - JOUR
T1 - Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
A1 - Zhengzhou CAO
A1 - Guozhu LIU
A1 - Yanfei ZHANG
A1 - Yueer SHAN
A1 - Yuting XU
J0 - Journal of Zhejiang University Science C
VL - -1
IS - -1
SP -
EP -
%@ 2095-9184
Y1 - 1998
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2300454
Abstract: This article proposes a kind of programmable logic element (PLE) based on sense-Switch pFLASH technology. By programming sense-Switch pFLASH, all 3-bit look-up table (LUT3) functions, partial LUT4 functions, latch functions, and DFF functions with enable and reset can be realized. Because the PLE uses a choice of operational logic (COOL) approach to the operation of logical functions, it allows any logic circuit to be implemented using any combinatorial logic and register ratio. This intrinsic property makes it close to the basic ASIC cell in terms of fine granularity, thus allowing ASIC-like cell-based mappers to apply all their optimization potential. By measuring sense-Switch pFLASH and PLE circuits, the results show that the "on" state driving current of the sense-Switch pFLASH is about 245.52 μA, and the "off" state leakage current is about 0.1 pA. The programmable function of PLE works normally. The delay of the typical combinatorial logic operation AND3 is 0.69 nS, and the delay of the sequential logic operation DFF is 0.65 nS, both of which meet the requirements of the design technical index.
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