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CLC number: TN911

On-line Access: 2021-08-17

Received: 2020-07-05

Revision Accepted: 2020-12-26

Crosschecked: 2021-06-08

Cited: 0

Clicked: 2554

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Yang Liu

https://orcid.org/0000-0001-8541-8104

Jie Li

https://orcid.org/0000-0002-6488-3696

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Frontiers of Information Technology & Electronic Engineering  2021 Vol.22 No.8 P.1127-1139

http://doi.org/10.1631/FITEE.2000323


A BCH error correction scheme applied to FPGA with embedded memory


Author(s):  Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li

Affiliation(s):  National Key Laboratory for Electronic Measurement Technology, North University of China, Taiyuan 030051, China; more

Corresponding email(s):   lylyly357@163.com, lijie@nuc.edu.cn

Key Words:  Error correction algorithm, Bose–, Chaudhuri–Hocquenghem (BCH) code, Field programmable gate array (FPGA), NAND flash


Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li. A BCH error correction scheme applied to FPGA with embedded memory[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(8): 1127-1139.

@article{title="A BCH error correction scheme applied to FPGA with embedded memory",
author="Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="22",
number="8",
pages="1127-1139",
year="2021",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2000323"
}

%0 Journal Article
%T A BCH error correction scheme applied to FPGA with embedded memory
%A Yang Liu
%A Jie Li
%A Han Wang
%A Debiao Zhang
%A Kaiqiang Feng
%A Jinqiang Li
%J Frontiers of Information Technology & Electronic Engineering
%V 22
%N 8
%P 1127-1139
%@ 2095-9184
%D 2021
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2000323

TY - JOUR
T1 - A BCH error correction scheme applied to FPGA with embedded memory
A1 - Yang Liu
A1 - Jie Li
A1 - Han Wang
A1 - Debiao Zhang
A1 - Kaiqiang Feng
A1 - Jinqiang Li
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 22
IS - 8
SP - 1127
EP - 1139
%@ 2095-9184
Y1 - 2021
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2000323


Abstract: 
Given the potential for bit flipping of data on a memory medium, a high-speed parallel bose–Chaudhuri–Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

一种应用于带有嵌入式存储器的FPGA的BCH纠错方案

刘洋1,李杰1,王瀚1,张德彪1,冯凯强1,李金强2
1中北大学电子测量技术国家重点实验室,中国太原市,030051
2山东航天电子技术研究所,中国烟台市,264000
摘要:鉴于存储介质上的数据存在位翻转的可能,提出一种模块化的、高速并行的Bose–Chaudhuri–Hocquenghem(BCH)纠错方案,该方案结合了逻辑实现和查找表。所提方案适用于具有片上嵌入式存储器的现场可编程门阵列的数据纠错。详细阐述了系统各部分的优化方法,并分析了该方案在BCH码信息位长度为1024位、码长为1068位且可纠正4位错误情况下的实现过程。

关键词:纠错算法;Bose–Chaudhuri–Hocquenghem(BCH)码;现场可编程门阵列(FPGA);闪存

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

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