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CLC number: TN919.3;TN929
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Received: 2002-07-06
Revision Accepted: 2002-11-21
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An efficient method for parallel CRC automatic generation
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CHEN Hong-sheng, ZHANG Wei-cheng, WANG Yong, CHEN Kang-sheng. An efficient method for parallel CRC automatic generation[J]. Journal of Zhejiang University Science A, 2003, 4(4): 433-436.
@article{title="An efficient method for parallel CRC automatic generation",
author="CHEN Hong-sheng, ZHANG Wei-cheng, WANG Yong, CHEN Kang-sheng",
journal="Journal of Zhejiang University Science A",
volume="4",
number="4",
pages="433-436",
year="2003",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.2003.0433"
}
%0 Journal Article
%T An efficient method for parallel CRC automatic generation
%A CHEN Hong-sheng
%A ZHANG Wei-cheng
%A WANG Yong
%A CHEN Kang-sheng
%J Journal of Zhejiang University SCIENCE A
%V 4
%N 4
%P 433-436
%@ 1869-1951
%D 2003
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.2003.0433
TY - JOUR
T1 - An efficient method for parallel CRC automatic generation
A1 - CHEN Hong-sheng
A1 - ZHANG Wei-cheng
A1 - WANG Yong
A1 - CHEN Kang-sheng
J0 - Journal of Zhejiang University Science A
VL - 4
IS - 4
SP - 433
EP - 436
%@ 1869-1951
Y1 - 2003
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.2003.0433
Abstract: The state Transition Equation (STE) based method to automatically generate the parallel CRC circuits for any generator polynomial or required amount of parallelism is presented. The parallel CRC circuit so generated is partially optimized before being fed to synthesis tools and works properly in our LAN transceiver. Compared with the cascading method, the proposed method gives better timing results and significantly reduces the synthesis time, in particular.
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