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index	Title
1	Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-... Author(s):Ying-hui Zhong, Shu-xiang Sun, Wen...  Clicked:5989  Download:2479  Cited:0  <Full Text>  <PPT> 2011 Frontiers of Information Technology & Electronic Engineering  2017 Vol.18 No.8 P.1180-1185  DOI:10.1631/FITEE.1601121
2	Iris: a multi-constraint graphic layout generation system Author(s):Liuqing CHEN, Qianzhi JING, Yixin ...  Clicked:813  Download:694  Cited:0  <Full Text>  <PPT> 152 Frontiers of Information Technology & Electronic Engineering  2024 Vol.25 No.7 P.968-987  DOI:10.1631/FITEE.2300312

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