CLC number: TN919.3;TN929
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 0000-00-00
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CHEN Hong-sheng, ZHANG Wei-cheng, WANG Yong, CHEN Kang-sheng. An efficient method for parallel CRC automatic generation[J]. Journal of Zhejiang University Science A, 2003, 4(4): 433-436.
@article{title="An efficient method for parallel CRC automatic generation",
author="CHEN Hong-sheng, ZHANG Wei-cheng, WANG Yong, CHEN Kang-sheng",
journal="Journal of Zhejiang University Science A",
volume="4",
number="4",
pages="433-436",
year="2003",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.2003.0433"
}
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%J Journal of Zhejiang University SCIENCE A
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%DOI 10.1631/jzus.2003.0433
TY - JOUR
T1 - An efficient method for parallel CRC automatic generation
A1 - CHEN Hong-sheng
A1 - ZHANG Wei-cheng
A1 - WANG Yong
A1 - CHEN Kang-sheng
J0 - Journal of Zhejiang University Science A
VL - 4
IS - 4
SP - 433
EP - 436
%@ 1869-1951
Y1 - 2003
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.2003.0433
Abstract: The state Transition Equation (STE) based method to automatically generate the parallel CRC circuits for any generator polynomial or required amount of parallelism is presented. The parallel CRC circuit so generated is partially optimized before being fed to synthesis tools and works properly in our LAN transceiver. Compared with the cascading method, the proposed method gives better timing results and significantly reduces the synthesis time, in particular.
[1]Glaise, R.J. and Jacquart, X.,1993. Fast CRC Calculation. IEEE International Conference on Computer Design: VLSI in Computers and Processors, p.602-605.
[2]Matsushima, T.K., Matsushima, T. and Hirasawa, S., 1996. Parallel encoder and decoder architecture for cyclic codes. IEICE Transactions fundamentals, E79-A(9):1313-1323.
[3]Pandeya, A.K. and Cassa, T.J., 1975. Parallel CRC Lets many lines use one circuit. Computer Design, 14(9):87-91.
[4]Perez, A., 1983. Byte-wise CRC calculation. IEEE Micro, 3(3):40-50.
[5]Pei, T.B. and Zukowski, C., 1992. High-speed parallel CRC circuits in VLSI. IEEE Trans. Comm.,40(4):653-657.
[6]Ramabadran, T.V. and Gaitonde, S.S., 1988. A tutorial on CRC computations. IEEE Micro, 8(4):62-75.
[7]Sarwate, D.V., 1988. Computation of cyclic redundancy Checks via table loop-up. Communications of the ACM, 31(8): 1008-1013.
[8]Sprachmann, M., 2001. Automatic generation of parallel CRC cricuits. IEEE Design & Test of Computer, 18(3):108-114.
[9]Ying, J., 2000. Research on computer-aided prototyping system and software evolution. Journal of Zhejiang University SCIENCE, 1(4): 384-387.
[10]IEEE Computer Society Technical committee on Computer Communications, 2000 Edition. IEEE Standards for Local Area Networks: Carrier Sense Multiple Access with Collision Detection (CSMA/CD): Media Access Control Frame Structure.
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