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CLC number: TP309
On-line Access: 2021-11-15
Received: 2020-12-09
Revision Accepted: 2021-03-08
Crosschecked: 2021-10-12
Cited: 0
Clicked: 5633
Citations: Bibtex RefMan EndNote GB/T7714
Implementation of PRINCE with resource-efficient structures based on FPGAs
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Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li. Implementation of PRINCE with resource-efficient structures based on FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(11): 1505-1516.
@article{title="Implementation of PRINCE with resource-efficient structures based on FPGAs",
author="Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="22",
number="11",
pages="1505-1516",
year="2021",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2000688"
}
%0 Journal Article
%T Implementation of PRINCE with resource-efficient structures based on FPGAs
%A Lang Li
%A Jingya Feng
%A Botao Liu
%A Ying Guo
%A Qiuping Li
%J Frontiers of Information Technology & Electronic Engineering
%V 22
%N 11
%P 1505-1516
%@ 2095-9184
%D 2021
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2000688
TY - JOUR
T1 - Implementation of PRINCE with resource-efficient structures based on FPGAs
A1 - Lang Li
A1 - Jingya Feng
A1 - Botao Liu
A1 - Ying Guo
A1 - Qiuping Li
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 22
IS - 11
SP - 1505
EP - 1516
%@ 2095-9184
Y1 - 2021
PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.2000688
Abstract: In this era of pervasive computing, low-resource devices have been deployed in various fields. PRINCE is a lightweight block cipher designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for PRINCE components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components, we propose three new hardware architectures for PRINCE. The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, low-cost, and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The low-cost architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of PRINCE, the new low-cost architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight, latency-critical applications.
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