Full Text:
<6312>
Summary: 
<1330>
CLC number: TP309
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2021-10-12
Cited: 0
Clicked: 6384
Citations: Bibtex RefMan EndNote GB/T7714
Implementation of PRINCE with resource-efficient structures based on FPGAs
| ||||||||||||||
Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li. Implementation of PRINCE with resource-efficient structures based on FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(11): 1505-1516.
@article{title="Implementation of PRINCE with resource-efficient structures based on FPGAs",
author="Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="22",
number="11",
pages="1505-1516",
year="2021",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2000688"
}
%0 Journal Article
%T Implementation of PRINCE with resource-efficient structures based on FPGAs
%A Lang Li
%A Jingya Feng
%A Botao Liu
%A Ying Guo
%A Qiuping Li
%J Frontiers of Information Technology & Electronic Engineering
%V 22
%N 11
%P 1505-1516
%@ 2095-9184
%D 2021
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2000688
TY - JOUR
T1 - Implementation of PRINCE with resource-efficient structures based on FPGAs
A1 - Lang Li
A1 - Jingya Feng
A1 - Botao Liu
A1 - Ying Guo
A1 - Qiuping Li
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 22
IS - 11
SP - 1505
EP - 1516
%@ 2095-9184
Y1 - 2021
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2000688
Abstract: In this era of pervasive computing, low-resource devices have been deployed in various fields. PRINCE is a lightweight block cipher designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for PRINCE components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components, we propose three new hardware architectures for PRINCE. The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, low-cost, and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The low-cost architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of PRINCE, the new low-cost architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight, latency-critical applications.
[1]Abbas YA, Jidin R, Jamil N, et al., 2014. Implementation of PRINCE algorithm in FPGA. Proc 6th Int Conf on Information Technology and Multimedia, p.1-4.
[2]Abbas YA, Jidin R, Jamil N, et al., 2015. PRINCE IP-core on field programmable gate arrays (FPGA). Res J Appl Sci Eng Technol, 10(8):914-922.
[3]Abbas YA, Jidin R, Jamil N, et al., 2016. Lightweight PRINCE algorithm IP core for securing GSM messaging using FPGA. Res J Inform Technol, 8(1):17-28.
[4]Abed S, Jaffal R, Mohd B, et al., 2019. FPGA modeling and optimization of a SIMON lightweight block cipher. Sensors, 19(4):913.
[5]Alioto M, 2017. Enabling the Internet of Things: from Integrated Circuits to Integrated Systems. Springer, Switzerland.
[6]Ayesha N, Singh P, Acharya B, 2020. An area-optimized architecture for LiCi cipher. Int Conf on Nanoelectronics, Circuits and Communication Systems, p.157-167.
[7]Balderas-Contreras T, Cumplido R, Feregrino-Uribe C, 2008. On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm. Comput Electr Eng, 34(6):531-546.
[8]Bansod G, Pisharoty N, Patil A, 2017. BORON: an ultra-lightweight and low power encryption design for pervasive computing. Front Inform Technol Electron Eng, 18(3):317-331.
[9]Beaulieu R, Shors D, Smith J, et al., 2015. The SIMON and SPECK lightweight block ciphers. Proc 52nd Annual Design Automation Conf, p.1-6.
[10]Bogdanov A, Knudsen LR, Leander G, et al., 2007. PRESENT: an ultra-lightweight block cipher. Proc 9th Int Workshop on Cryptographic Hardware and Embedded Systems, p.450-466.
[11]Borghoff J, Canteaut A, Güneysu T, et al., 2012. PRINCE—a low-latency block cipher for pervasive computing applications. Proc 18th Int Conf on the Theory and Application of Cryptology and Information Security, p.208-225.
[12]Dahiphale V, Raut H, Bansod G, 2019. Design and implementation of novel datapath designs of lightweight cipher RECTANGLE for resource constrained environment. Multim Tools Appl, 78(16):23659-23688.
[13]Dahiphale V, Bansod G, Zambare A, et al., 2020. Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA. Front Inform Technol Electron Eng, 21(4):615-628.
[14]Dhanda S, Singh B, Jindal P, 2020. Lightweight cryptography: a solution to secure IoT. Wirel Pers Commun, 112(3):947-1980.
[15]Feizi S, Nemati A, Ahmadi A, et al., 2015. A high-speed FPGA implementation of a bit-slice ultra-lightweight block cipher, RECTANGLE. Proc 5th Int Conf on Computer and Knowledge Engineering, p.206-211.
[16]Kitsos P, Sklavos N, Parousi M, et al., 2012. A comparative study of hardware architectures for lightweight block ciphers. Comput Electr Eng, 38(1):148-160.
[17]Lara-Nino CA, Díaz-Pérez A, Morales-Sandoval M, 2018. FPGA-based assessment of Midori and GIFT lightweight block ciphers. Proc 20th Int Conf on Information and Communications Security, p.745-755.
[18]Liu BT, Li L, Wu RX, et al., 2019. Loong: a family of involutional lightweight block cipher based on SPN structure. IEEE Access, 7:36023-136035.
[19]Maene P, Verbauwhede I, 2015. Single-cycle implementations of block ciphers. Proc 4th Int Workshop on Lightweight Cryptography for Security and Privacy, p.131-147.
[20]Philip MA, Vaithiyanathan AV, 2017. A survey on lightweight ciphers for IoT devices. Int Conf on Technological Advancements in Power and Energy, p.1-4.
[21]Rashidi B, 2019. High-throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers. Int J Circ Theor Appl, 47(8):1254-1268.
[22]Rashidi B, 2020a. Flexible structures of lightweight block ciphers PRESENT, SIMON and LED. IET Circ Dev Syst, 14(3):369-380.
[23]Rashidi B, 2020b. Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher. Int J Circ Theory Appl, 48(8):1227-1243.
[24]Shrivastava N, Singh P, Acharya B, 2020. A novel hardware architecture for rectangle block cipher. Int Conf on Nanoelectronics, Circuits and Communication Systems, p.169-181.
[25]Singh P, Acharya B, Chaurasiya RK, 2019. Efficient VLSI architectures of LILLIPUT block cipher for resource-constrained RFID devices. IEEE Int Conf on Electronics, Computing and Communication Technologies, p.1-6.
[26]Wu WL, Zhang L, 2011. LBlock: a lightweight block cipher. Proc 9th Int Conf on Applied Cryptography and Network Security, p.327-344.
[27]Xiong JB, Ren J, Chen L, et al., 2019. Enhancing privacy and availability for data clustering in intelligent electrical service of IoT. IEEE Int Things J, 6(2):530-1540.
[28]Xu T, Wendt JB, Potkonjak M, 2014. Security of IoT systems: design challenges and opportunities. IEEE/ACM Int Conf on Computer-Aided Design, p.417-423.
[29]Yang GQ, Zhu B, Suder V, et al., 2015. The Simeck family of lightweight block ciphers. Int Workshop on Cryptographic Hardware and Embedded Systems, p.307-329.
[30]Zhang WT, Bao ZZ, Lin DD, et al., 2015. RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms. Sci China Inform Sci, 58(12):122103:1-122103:15.
ORCID: 
Open peer comments: Debate/Discuss/Question/Opinion
<1>