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Received: 2002-05-03
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Noise and linearity optimization methods for a 1.9GHz low noise amplifier
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GUO Wei, HUANG Da-quan. Noise and linearity optimization methods for a 1.9GHz low noise amplifier[J]. Journal of Zhejiang University Science A, 2003, 4(3): 281-286.
@article{title="Noise and linearity optimization methods for a 1.9GHz low noise amplifier",
author="GUO Wei, HUANG Da-quan",
journal="Journal of Zhejiang University Science A",
volume="4",
number="3",
pages="281-286",
year="2003",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.2003.0281"
}
%0 Journal Article
%T Noise and linearity optimization methods for a 1.9GHz low noise amplifier
%A GUO Wei
%A HUANG Da-quan
%J Journal of Zhejiang University SCIENCE A
%V 4
%N 3
%P 281-286
%@ 1869-1951
%D 2003
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.2003.0281
TY - JOUR
T1 - Noise and linearity optimization methods for a 1.9GHz low noise amplifier
A1 - GUO Wei
A1 - HUANG Da-quan
J0 - Journal of Zhejiang University Science A
VL - 4
IS - 3
SP - 281
EP - 286
%@ 1869-1951
Y1 - 2003
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.2003.0281
Abstract: noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.
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