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CLC number: TN851
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
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DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers
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GUAN Yun-feng, ZHANG Zhao-yang, Lai Li-feng. DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers[J]. Journal of Zhejiang University Science A, 2003, 4(5): 526-531.
@article{title="DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers",
author="GUAN Yun-feng, ZHANG Zhao-yang, Lai Li-feng",
journal="Journal of Zhejiang University Science A",
volume="4",
number="5",
pages="526-531",
year="2003",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.2003.0526"
}
%0 Journal Article
%T DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers
%A GUAN Yun-feng
%A ZHANG Zhao-yang
%A Lai Li-feng
%J Journal of Zhejiang University SCIENCE A
%V 4
%N 5
%P 526-531
%@ 1869-1951
%D 2003
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.2003.0526
TY - JOUR
T1 - DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers
A1 - GUAN Yun-feng
A1 - ZHANG Zhao-yang
A1 - Lai Li-feng
J0 - Journal of Zhejiang University Science A
VL - 4
IS - 5
SP - 526
EP - 531
%@ 1869-1951
Y1 - 2003
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.2003.0526
Abstract: This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.
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