Full Text:
<3068>
CLC number: TP302
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2011-07-06
Cited: 1
Clicked: 7232
A power-aware code-compression design for RISC/VLIW architecture
| |||||||||||||
Che-Wei Lin, Chang Hong Lin, Wei Jhih Wang. A power-aware code-compression design for RISC/VLIW architecture[J]. Journal of Zhejiang University Science C, 2011, 12(8): 629-637.
@article{title="A power-aware code-compression design for RISC/VLIW architecture",
author="Che-Wei Lin, Chang Hong Lin, Wei Jhih Wang",
journal="Journal of Zhejiang University Science C",
volume="12",
number="8",
pages="629-637",
year="2011",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1000321"
}
%0 Journal Article
%T A power-aware code-compression design for RISC/VLIW architecture
%A Che-Wei Lin
%A Chang Hong Lin
%A Wei Jhih Wang
%J Journal of Zhejiang University SCIENCE C
%V 12
%N 8
%P 629-637
%@ 1869-1951
%D 2011
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1000321
TY - JOUR
T1 - A power-aware code-compression design for RISC/VLIW architecture
A1 - Che-Wei Lin
A1 - Chang Hong Lin
A1 - Wei Jhih Wang
J0 - Journal of Zhejiang University Science C
VL - 12
IS - 8
SP - 629
EP - 637
%@ 1869-1951
Y1 - 2011
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1000321
Abstract: We studied the architecture of embedded computing systems from the viewpoint of power consumption in memory systems and used a selective-code-compression (SCC) approach to realize our design. Based on the LZW (Lempel-Ziv-Welch) compression algorithm, we propose a novel cost effective compression and decompression method. The goal of our study was to develop a new SCC approach with an extended decision policy based on the prediction of power consumption. Our decompression method had to be easily implemented in hardware and to collaborate with the embedded processor. The hardware implementation of our decompression engine uses the TSMC 0.18 μm-2p6m model and its cell-based libraries. To calculate power consumption more accurately, we used a static analysis method to estimate the power overhead of the decompression engine. We also used variable sized branch blocks and considered several features of very long instruction word (VLIW) processors for our compression, including the instruction level parallelism (ILP) technique and the scheduling of instructions. Our code-compression methods are not limited to VLIW machines, and can be applied to other kinds of reduced instruction set computer (RISC) architecture.
[1]Benini, L., Menichelli, F., Olivieri, M., 2004. A class of code compression schemes for reducing power consumption in embedded microprocessor systems. IEEE Trans. Comput., 53(4):467-482.
[2]Bonny, T., Henkel, J., 2009. LICT: Left-Uncompressed Instructions Compression Technique to Improve the Decoding Performance of VLIW Processors. ACM Design Automation Conf., p.903-906.
[3]Brooks, D., Tiwari, V., Martonosi, M., 2000. Wattch: a framework for architectural-level power analysis and optimizations. ACM SIGARCH Comput. Archit. News, 28(2):83-94.
[4]Burger, D., Austin, M., 1994. SimpleScalar User’s Guide: the SimpleScalar Tool Set, Version 2.0.
[5]Cuppu, V., 1999. Cycle Accurate Simulator for TMS320C62x, 8 Way VLIW DSP Processor. University of Maryland, College Park.
[6]IBM, 1998. PowerPC Code Compression Utility User’s Manual, Version 3.0.
[7]Lefurgy, C., Bird, P., Chen, I., Mudge, T., 1997. Improving Code Density Using Compression Techniques. Proc. 30th Annual Int. Symp. on Microarchitecture, p.194-203.
[8]Lekatsas, H., Wolf, W., 1999. SAMC: a code compression algorithm for embedded processors. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 18(12):1689-1701.
[9]Liao, S., Devadas, S., Keutzer, K., 1995. Code Density Optimization for Embedded DSP Processors Using Data Compression Techniques. Conf. on Advanced Research in VLSI, p.272-285.
[10]Lin, C.H., Xie, Y., Wolf, W., 2004. LZW-Based Code Compression for VLIW Embedded Systems. Design, Automation and Test in Europe Conf. and Exposition, p.76-81.
[11]Lin, C.H., Xie, Y., Wolf, W., 2007. Code compression for VLIW embedded systems using a self-generating table. IEEE Trans. VLSI Syst., 15(10):1160-1171.
[12]Netto, E.W., Azevedo, R., Centoducatte, P., Araujo, G., 2004. Multi-profile Based Code Compression. ACM Design Automation Conf., p.244-249.
[13]Segars, S., Clarke, K., Goudge, L., 1995. Embedded controlproblems, Thumb and the ARM7TDMI. IEEE Micro, 15(5):22-30.
[14]Seong, S., Mishra, P., 2008. A bitmask-based code compression technique for embedded systems. IEEE Trans. Comput., 27(4):673-685.
[15]Synopsys, 2006. PrimePower Manual, Version Y-2006.06.
[16]Synopsys, 2007a. Design Compiler Reference Manual: Constraints and Timing, Version A-2007.12.
[17]Synopsys, 2007b. Astro User Guide, Version Z-2007.03.
[18]Synplicity, 2005. Synplicity FPGA Synthesis Synplify, Synplify Pro, Synplify Premier, and Synplify Premier with Design Planner: User Guide.
[19]TI, 2006. TMS320C62xx CPU and Instruction Set: Reference Guide, SPRU731.
[20]TI, 2008a. TMS320C64x/C64x+ DSP CPU and Instruction Set: Reference Guide, SPRU732H.
[21]TI, 2008b. TMS320C6000 Optimizing Compiler v6.1: User’s Guide, SPRU1870.
[22]Wolfe, A., Chanin, A., 1992. Executing Compressed Programs on an Embedded RISC Architecture. Int. Symp. on Microarchitecture, p.81-91.
[23]Xie, Y., Wolf, W., Lekatsas, H., 2002. Code Compression for VLIW Using Variable-to-Fixed Coding. ACM Int. Symp. on System Synthesis, p.138-143.
[24]Xie, Y., Wolf, W., Lekatsas, H., 2003. Profile-Driven Selective Code Compression. Design, Automation and Test in Europe Conf. and Exposition, p.462-467.
[25]Yang, L., Zhang, T., Wang, D., Hou, C., 2009. Optimal-Partition Based Code Compression for Embedded Processor. IEEE 8th Int. Conf. on ASIC, p.87-90.
Open peer comments: Debate/Discuss/Question/Opinion
<1>