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Abstract: High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control (TTC) system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper, we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays (FPGAs). First, we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second, we use the internal alignment circuit of the transceiver and a digital clock manager (DCM)/phase-locked loop (PLL) based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions, our design not only implements fixed chip latency, but also reduces the average system lock time.

[1]Aliaga, R.J., Monzo, J.M., Spaggiari, M., et al., 2011. PET system synchronization and timing resolution using high-speed data links. IEEE Trans. Nucl. Sci., 58(4):1596-1605.

[2]Aloisio, A., Cevenini, F., Giordano, R., et al., 2009. High-speed, fixed-latency serial links with FPGAs for synchronous transfers. IEEE Trans. Nucl. Sci., 56(5):2864-2873.

[3]Aloisio, A., Cevenini, F., Giordano, R., et al., 2010. Emulating the GLink chip set with FPGA serial transceivers in the ATLAS Level-1 Muon trigger. IEEE Trans. Nucl. Sci., 57(2):467-471.

[4]Aloisio, A., Ameli, F., Bocci, V., et al., 2013. Design, implementation and test of the timing trigger and control receiver for the LHC. J. Instrum., 8(2):T02003.

[5]Giordano, R., Aloisio, A., 2011. Fixed-latency, multi-gigabit serial links with Xilinx FPGAs. IEEE Trans. Nucl. Sci., 58(1):194-201.

[6]Giordano, R., Aloisio, A., 2012. Protocol-independent, fixed-latency links with FPGA-embedded SerDeses. J. Instrum., 7(5):P05004.

[7]Lemke, F., Slogsnat, D., Burkhardt, N., et al., 2010. A unified DAQ interconnection network with precise time synchronization. IEEE Trans. Nucl. Sci., 57(2):412-418.

[8]Le-Provost, H., Moudden, Y., Anvar, S., et al., 2011. A readout system-on-chip for a cubic kilometer submarine neutrino telescope. J. Instrum., 6(12):C12044.

[9]Moreira, P., Marchioro, A., Kloukinas, K., 2007. The GBT: a proposed architecture for multi-Gb/s data transmission in high energy physics. Proc. Topical Workshop on Electronics for Particle Physics, p.332-336.

[10]Taylor, B.G., 1998. TTC distribution for LHC detectors. IEEE Trans. Nucl. Sci., 45(3):821-828.

[11]Texas Instruments (TI), 2013. SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement. Available from http://www.ti.com.cn/cn/lit/ds/symlink/scan25100.pdf

[12]Widmer, A.X., Franaszek, P.A., 1983. A DC-balanced, partitioned-block, 8b/10b transmission code. IBM J. Res. Devel., 27(5):440-451.

[13]Xilinx, 2009a. UG196 Virtex-5 FPGA RocketIO GTP Transceiver User Guide v2.1. Available from http://www.xilinx.com/support/documentation/user_guides/ug196.pdf

[14]Xilinx, 2009b. UG198 Virtex-5 FPGA RocketIO GTX Transceiver User Guide v3.0. Available from http://www.xilinx.com/support/documentation/user_guides/ug198.pdf

[15]Xilinx, 2011. UG347 ML505/ML506/ML507 Evaluation Platform User Guide v3.1.2. Available from http://www.xilinx.com/support/documentation/boards_and_kits/ug347.pdf

[16]Xilinx, 2012. UG190 Virtex-5 FPGA User Guide v5.4. Available from http://www.xilinx.com/support/documentation/user_guides/ug190.pdf