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CLC number: TP309; TP333

On-line Access: 2024-08-27

Received: 2023-10-17

Revision Accepted: 2024-05-08

Crosschecked: 2018-07-08

Cited: 0

Clicked: 7074

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Fang-ting Huang

http://orcid.org/0000-0001-7887-8735

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Frontiers of Information Technology & Electronic Engineering  2018 Vol.19 No.7 P.847-863

http://doi.org/10.1631/FITEE.1601652


Enhancing security of NVM-based main memory with dynamic Feistel network mapping


Author(s):  Fang-ting Huang, Dan Feng, Wen Xia, Wen Zhou, Yu-cheng Zhang, Min Fu, Chun-tao Jiang, Yu-kun Zhou

Affiliation(s):  Wuhan National Laboratory for Optoelectronics, Wuhan 430074, China; more

Corresponding email(s):   dfeng@hust.edu.cn

Key Words:  Non-volatile memory (NVM), Endurance, Wear leveling, Timing attack


Fang-ting Huang, Dan Feng, Wen Xia, Wen Zhou, Yu-cheng Zhang, Min Fu, Chun-tao Jiang, Yu-kun Zhou. Enhancing security of NVM-based main memory with dynamic Feistel network mapping[J]. Frontiers of Information Technology & Electronic Engineering, 2018, 19(7): 847-863.

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Abstract: 
As promising alternatives in building future main memory systems, emerging non-volatile memory (NVM) technologies can increase memory capacity in a cost-effective and power-efficient way. However, NVM is facing security threats due to its limited write endurance: a malicious adversary can wear out the cells and cause the NVM system to fail quickly. To address this issue, several wear-leveling schemes have been proposed to evenly distribute write traffic in a security-aware manner. In this study, we present a new type of timing attack, remapping timing attack (RTA), based on information leakage from the remapping latency difference in NVM. Our analysis and experimental results show that RTA can cause three of the latest wear-leveling schemes (i.e., region-based start-gap, security refresh, and multi-way wear leveling) to lose their effectiveness in several days (even minutes), causing failure of NVM. To defend against such an attack, we further propose a novel wear-leveling scheme called the ‘security region-based start-gap (security RBSG)’, which is a two-stage strategy using a dynamic Feistel network to enhance the simple start-gap wear leveling with level-adjustable security assurance. The theoretical analysis and evaluation results show that the proposed security RBSG not only performs well when facing traditional malicious attacks, but also better defends against RTA.

基于Feistel动态网络映射的非易失存储内存安全增强方法

概要:作为构建未来主存系统的替代方案,新兴的非易失性存储器NVM(non-volatile memory)技术可用高能效和低开销方式提高内存容量。然而,非易失存储器有限的耐久性导致其面临安全威胁:若恶意攻击者持续对一小部分物理行进行写操作,整个系统会很快失效。为解决该问题,提出几个磨损均衡方案,以安全感知的方式将写负载均匀分布到整个内存空间。提出一种基于重映射时间差异信息泄露的时间探测攻击RTA(remapping timing attack)。分析和实验结果表明,RTA可攻击3种最新磨损均衡方案(例如,基于区域的start-gap、安全刷新和多路磨损均衡),使它们在很短时间内失效(例如,几天甚至几分钟)。为抵抗该攻击,提出一种新的磨损均衡方案,即基于安全区域的start-gap(security RBSG)。该方案采用动态Feistel网络的两级策略,利用可调节安全保障增强简单的start-gap。理论分析和评估结果表明,提出的安全RBSG方案不仅可以抵抗传统攻击,也可以很好地抵抗RTA。

关键词:非易失存储(NVM);耐久性;磨损均衡;时间攻击

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Reference

[1]Binkert N, Beckmann B, Black G, et al., 2011. The gem5 simulator. ACM SIGARCH Comput Archit News, 39(2):1-7.

[2]Bishnoi R, Ebrahimi M, Oboril F, et al., 2014. Asynchronous asymmetrical write termination (AAWT) for a low power STT-MRAM. Design, Automation & Test in Europe Conf & Exhibition, p.1-6.

[3]Cho S, Lee H, 2009. Flip-N-write: a simple deterministic technique to improve PRAM write performance, energy and endurance. Proc 42nd Annual IEEE/ACM Int Symp on Microarchitecture, p.347-357.

[4]Chung H, Jeong BH, Min BJ, et al., 2011. A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW. IEEE Int Solid-State Circuits Conf, p.500-502.

[5]Freitas RF, Wilcke WW, 2008. Storage-class memory: the next storage system technology. IBM J Res Dev, 52(4-5):439-447.

[6]Gal E, Toledo S, 2005. Algorithms and data structures for flash memories. ACM Comput Surv, 37(2):138-163.

[7]Gove D, 2007. CPU2006 working set size. ACM SIGARCH Comput Archit News, 35(1):90-96.

[8]Huai Y, 2008. Spin-transfer torque MRAM (STT-MRAM): challenges and prospects. AAPPS Bull, 18(6):33-40.

[9]Huang F, Feng D, Xia W, et al., 2016. Security RBSG: protecting phase change memory with security-level adjustable dynamic mapping. IEEE Int Parallel and Distributed Processing Symp, p.1081-1090.

[10]Kim YB, Lee SR, Lee D, et al., 2011. Bi-layered RRAM with unlimited endurance and extremely uniform switching. Symp on VLSI Technology, p.52-53.

[11]Li Z, Wang F, Hua Y, et al., 2016. Exploiting more parallelism from write operations on PCM. Design, Automation & Test in Europe Conf & Exhibition, p.768-773.

[12]Liddicoat AA, Flynn MJ, 2000. Parallel square and cube computations. Conf Record of the 34th Asilomar Conf on Signals, Systems and Computers, p.1325-1329.

[13]Menezes AJ, van Oorschot PC, Vanstone SA, 1996. Handbook of Applied Cryptography. CRC Press, Boca Raton, USA, p.683.

[14]Micron Inc., 2011. Micron 128Mb P8P Parallel PCM Data Sheet.

[15]Mittal S, Vetter JS, 2016. A survey of software techniques for using non-volatile memories for storage and main memory systems. IEEE Trans Parall Distr Syst, 27(5):1537-1550.

[16]Mittal S, Vetter JS, Li D, 2015. A survey of architectural approaches for managing embedded dram and non-volatile on-chip caches. IEEE Trans Parall Distr Syst, 26(6):1524-1537.

[17]Palangappa PM, Mohanram K, 2016. CompEx: compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM. IEEE Int Symp on High Performance Computer Architecture, p.90-101.

[18]Qureshi MK, Karidis J, Franceschini M, et al., 2009. Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. Proc 42nd Annual IEEE/ACM Int Symp on Microarchitecture, p.14-23.

[19]Qureshi MK, Seznec A, Lastras LA, et al., 2011. Practical and secure PCM systems by online detection of malicious write streams. IEEE 17th Int Symp on High Performance Computer Architecture, p.478-489.

[20]Qureshi MK, Franceschini MM, Jagmohan A, et al., 2012. PreSET: improving performance of phase change memories by exploiting asymmetry in write times. ACM SIGARCH Comput Archit News, 40(3):380-391.

[21]Seznec A, 2009. Towards Phase Change Memory as a Secure Main Memory. Technical Report, No. RR-7088, INRIA, Campus Universitaire de Beaulieu, Rennes.> 22 ACM SIGARCH Comput Archit News, 38(3):383-394.

[23]Yang BD, Lee JE, Kim JS, et al., 2007. A low power phase-change random access memory using a data-comparison write scheme. IEEE Int Symp on Circuits and Systems, p.3014-3017.

[24]Yu H, Du Y, 2014. {Increasing endurance and security of phase-change memory with multi-way wear-leveling}. IEEE Trans Comput, 63(5):1157-1168.

[25]Yun J, Lee S, Yoo S, 2012. Bloom filter-based dynamic wear leveling for phase-change RAM. Design, Automation & Test in Europe Conf &Exhibition, p.1513-1518.

[26]Zhou P, Zhao B, Yang J, et al., 2009. A durable and energy efficient main memory using phase change memory technology. ACM SIGARCH Comput Archit News, p.14-23.

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