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CLC number: TN43

On-line Access: 2022-06-17

Received: 2021-09-10

Revision Accepted: 2021-12-29

Crosschecked: 2022-06-20

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Citations:  Bibtex RefMan EndNote GB/T7714




Nabiollah SHIRI


Mahmood RAFIEE




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Frontiers of Information Technology & Electronic Engineering  2022 Vol.23 No.6 P.950-965


An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending

Author(s):  Ayoub SADEGHI, Nabiollah SHIRI, Mahmood RAFIEE, Mahsa TAHGHIGH

Affiliation(s):  Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz 71987-74731, Iran

Corresponding email(s):   na.shiri@iau.ac.ir

Key Words:  Full adder, Transmission gate, Counter, Multiplier, Three-dimensional layout, Image blending

Ayoub SADEGHI, Nabiollah SHIRI, Mahmood RAFIEE, Mahsa TAHGHIGH. An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending[J]. Frontiers of Information Technology & Electronic Engineering, 2022, 23(6): 950-965.

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publisher="Zhejiang University Press & Springer",

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%T An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending
%A Nabiollah SHIRI
%A Mahmood RAFIEE
%J Frontiers of Information Technology & Electronic Engineering
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%I Zhejiang University Press & Springer
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T1 - An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending
A1 - Ayoub SADEGHI
A1 - Nabiollah SHIRI
A1 - Mahmood RAFIEE
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 23
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EP - 965
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.2100432

We present a new counter-based Wallace-tree (CBW) 8×8 multiplier. The multiplier‍’‍s counters are implemented with a new hybrid full adder (FA) cell, which is based on the transmission gate (TG) technique. The proposed FA, TG-based AND gate, and hybrid half adder (HA) generate M:3 (4≤M≤7) digital counters with the ability to save at least 50% area occupation. Simulations by 90 nm technology prove the superiority of the proposed FA and digital counters under different conditions over the state-of-the-art designs. By using the proposed cells, the CBW multiplier exhibits high driving capability, low power consumption, and high speed. The CBW multiplier has a 0.0147 mm2 die area in a pad. The post-layout extraction proves the accuracy of experimental implementation. An image blending mechanism is proposed, in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW multiplier in image processing applications. The peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM) are calculated as image quality parameters, and the results confirm that the presented CBW multiplier can be used as an alternative to designs in the literature.


Ayoub SADEGHI, Nabiollah SHIRI, Mahmood RAFIEE, Mahsa TAHGHIGH
摘要:提出一种新的基于计数器的华莱士树(CBW)8×8乘法器。乘法器的计数器使用基于传输门技术的新型混合全加器单元。所提全加器、基于传输门的与门和混合半加器生成M:3(4≤M≤7)数字计数器,能够节省至少50%的面积。通过90 nm技术仿真证明所提全加器和数字计数器在不同条件下均优于当前最先进设计。通过使用所提单元,CBW乘法器表现出高驱动、低功耗和高速性能。CBW乘法器在焊盘中的芯片面积为0.0147 mm2。后布局提取证明了实验的准确性。同时提出一种图像融合机制,其中MATLAB和HSPICE之间的直接接口用于在图像处理应用中评估所提CBW乘法器。峰值信噪比和结构相似性指数度量被用作图像质量参数,结果证实所提CBW乘法器可以替代文献中的设计。


Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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