CLC number: TN43
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2022-07-05
Cited: 0
Clicked: 3486
Citations: Bibtex RefMan EndNote GB/T7714
https://orcid.org/0000-0001-9904-9813
https://orcid.org/0000-0003-4683-1814
Ayoub SADEGHI, Nabiollah SHIRI, Mahmood RAFIEE, Mahsa TAHGHIGH. An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending[J]. Frontiers of Information Technology & Electronic Engineering, 2022, 23(6): 950-965.
@article{title="An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending",
author="Ayoub SADEGHI, Nabiollah SHIRI, Mahmood RAFIEE, Mahsa TAHGHIGH",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="23",
number="6",
pages="950-965",
year="2022",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2100432"
}
%0 Journal Article
%T An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending
%A Ayoub SADEGHI
%A Nabiollah SHIRI
%A Mahmood RAFIEE
%A Mahsa TAHGHIGH
%J Frontiers of Information Technology & Electronic Engineering
%V 23
%N 6
%P 950-965
%@ 2095-9184
%D 2022
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2100432
TY - JOUR
T1 - An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending
A1 - Ayoub SADEGHI
A1 - Nabiollah SHIRI
A1 - Mahmood RAFIEE
A1 - Mahsa TAHGHIGH
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 23
IS - 6
SP - 950
EP - 965
%@ 2095-9184
Y1 - 2022
PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.2100432
Abstract: We present a new counter-based Wallace-tree (CBW) 8×8 multiplier. The multiplier’s counters are implemented with a new hybrid full adder (FA) cell, which is based on the transmission gate (TG) technique. The proposed FA, TG-based AND gate, and hybrid half adder (HA) generate M:3 (4≤M≤7) digital counters with the ability to save at least 50% area occupation. Simulations by 90 nm technology prove the superiority of the proposed FA and digital counters under different conditions over the state-of-the-art designs. By using the proposed cells, the CBW multiplier exhibits high driving capability, low power consumption, and high speed. The CBW multiplier has a 0.0147 mm2 die area in a pad. The post-layout extraction proves the accuracy of experimental implementation. An image blending mechanism is proposed, in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW multiplier in image processing applications. The peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM) are calculated as image quality parameters, and the results confirm that the presented CBW multiplier can be used as an alternative to designs in the literature.
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