CLC number: TN702
On-line Access: 2011-06-07
Received: 2010-06-27
Revision Accepted: 2010-09-10
Crosschecked: 2011-05-05
Cited: 3
Clicked: 9581
Mi Lin, Wei-feng L, Ling-ling Sun. Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit[J]. Journal of Zhejiang University Science C, 2011, 12(6): 507-514.
@article{title="Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit",
author="Mi Lin, Wei-feng L, Ling-ling Sun",
journal="Journal of Zhejiang University Science C",
volume="12",
number="6",
pages="507-514",
year="2011",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1000222"
}
%0 Journal Article
%T Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit
%A Mi Lin
%A Wei-feng L
%A Ling-ling Sun
%J Journal of Zhejiang University SCIENCE C
%V 12
%N 6
%P 507-514
%@ 1869-1951
%D 2011
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1000222
TY - JOUR
T1 - Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit
A1 - Mi Lin
A1 - Wei-feng L
A1 - Ling-ling Sun
J0 - Journal of Zhejiang University Science C
VL - 12
IS - 6
SP - 507
EP - 514
%@ 1869-1951
Y1 - 2011
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1000222
Abstract: The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD d flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD d flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTd flip-flop circuits.
[1]Avedillo, M.J., Quintana, J.M., Pettenghi, H., 2006. Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. IEEE Trans. Circ. Syst. II, 53(5):334-338.
[2]Berezowski, K.S., Vrudhula, S.B.K., 2005. Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. Eighth Euromicro Conf. on Digital System Design, p.139-142.
[3]Berezowski, K.S., Vrudhula, S.B.K., 2007. Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. 37th Int. Symp. on Multiple-Valued Logic, p.24-31.
[4]Bhattacharya, M., Kulkarni, S., Gonzalez, A., Mazumder, P., 2000. Prototyping Technique for Large-Scale RTD-CMOS Circuits. IEEE Int. Symp. on Circuits and Systems, p.635-638.
[5]Chen, K.J., Akeyoshi, T., Maezawa, K., 1995. Monolithic integration of resonant tunneling diodes and FET’s for monostable-bistable transition logic elements (MOBILE’s). IEEE Electron Dev. Lett., 16(2):70-73.
[6]Chen, X.X., Shen, J.Z., 2001. Resent Digital Theory. Zhejiang University Press, Hangzhou, China, p.149-150 (in Chinese).
[7]Choi, S., Lee, B., Kim, T., Yang, K., 2004. CML-type monostable bistable logic element (MOBILE) using InP-based monolithic RTD/HBT technology. Electron. Lett., 40(13):792-793.
[8]Ding, L., Mazumder, P., 2003. A Novel Application of Resonant Tunneling Device in High Performance Digital Circuits. Third IEEE Conf. on Nanotechnology, p.520-523.
[9]Drechsler, R., 1996. Verification of Multi-valued Logic Networks. IEEE Int. Symp. on Multiple-Valued Logic, p.10-15.
[10]Etiemble, D., Israel, M., 1988. Comparison of binary and multivalued ICs according to VLSI criteria. Computer, 21(4):28-42.
[11]González, A.F., Bhattacharya, M., Kulkarni, S., Mazumder, P., 2001. CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differential-resistance devices. IEEE J. Sol.-State Circ., 36(6):924-932.
[12]Hanyu, T., Kameyama, M., Higuchi, T., 1993. Beyond-Binary Circuits for Signal Processing. 40th IEEE Int. Solid-State Circuits Conf., p.134-135, 276-277.
[13]Hurst, S.L., 1984. Multiple-valued logic—its status and its future. IEEE Trans. Comput., C-33(12):1160-1179.
[14]Hurst, S.L., 1988. Two Decades of Multiple-Valued Logic—an Invited Tutorial. Proc. 18th Int. Symp. on Multiple-Valued Logic, p.164-175.
[15]Kameyama, M., 1990. Toward the Age of Beyond-Binary Electronics and Systems. Proc. 20th Int. Symp. on Multiple-Valued Logic, p.162-166.
[16]Li, S.R., Mazumder, P., Yang, K., 2005. On the Functional Failure and Switching Time Analysis of the MOBILE Circuit. IEEE Int. Symp. on Circuits and Systems, 3:2531-2534.
[17]Li, X.B., 2009. Digital monolithic integrated circuits based on RTTs. Micronanoelectron. Technol., 46(1):1-9 (in Chinese).
[18]Lin, M., Sun, Z.Y., Shen, J.Z., 2004. Design of NAND and NOR logic gates based on RTD. Bull. Sci. Technol., 20(5):434-437 (in Chinese).
[19]Lin, M., Lü, W.F., Sun, L.L., 2007. Design of ternary NAND and NOR gates based on resonant tunneling devices. J. Semicond., 28(12):1983-1987 (in Chinese).
[20]Maezawa, K., 2005. Resonant Tunneling Diodes and Their Application to High-Speed Circuits. IEEE Compound Semiconductor Integrated Circuit Symp., p.97-100.
[21]Mazumder, P., Kulkarni, S., Bhattacharya, M., Jian, P.S., Haddad, G.I., 1998. Digital circuit applications of resonant tunneling devices. Proc. IEEE, 86(4):664-686.
[22]Nunez, J., Quintana, J.M., Avedillo, M.J., 2007a. Correct DC Operation in RTD-Based Ternary Inverters. Second IEEE Int. Conf. on Nano/Micro Engineered and Molecular Systems, p.860-865.
[23]Nunez, J., Quintana, J.M., Avedillo, M.J., 2007b. Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. 37th Int. Symp. on Multiple-Valued Logic, p.51-56.
[24]Nunez, J., Quintana, J.M., Avedillo, M.J., 2008. Design of RTD-Based NMIN/NMAX Gates. Eighth IEEE Conf. on Nanotechnology, p.518-521.
[25]Quan, L.S., Quan, K., Qian, B.S., 2000. An optimization technique for the design of multiple valued PLA’s. Microelectronics, 30(6):406-409 (in Chinese).
[26]Quintana, J.M., Avedillo, M.J., Nunez, J., 2006. DC Correct Operation in MOBILE Inverters. 49th IEEE Int. Midwest Symp. on Circuits and Systems, p.479-483.
[27]Uemura, T., Baba, T., 2000. Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. Proc. 30th IEEE Int. Symp. on Multiple-Valued Logic, p.305-310.
[28]Uemura, T., Baba, T., 2001a. A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors. Proc. 31st IEEE Int. Symp. on Multiple-Valued Logic, p.89-93.
[29]Uemura, T., Baba, T., 2001b. A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors. IEEE Trans. Electron Dev., 49(8):1336-1340.
[30]Wu, X.W., 1994. The Design Theory of Multiple Logic Circuits. Hangzhou University Press, Hangzhou, China, p.25-27, 233-267 (in Chinese).
[31]Yamamoto, M., Matsuzaki, H., Itoh, T., Waho, T., Akeyoshi, T., Osaka, J., 1999. Ultrahigh-Speed Circuits Using Resonant Tunneling Devices. Proc. Ninth Great Lakes Symp. on VLSI, p.150-153.
[32]Yao, C.J., 2010. The ideas and methods of the three-valued logic. J. Beijing Inst. Technol. (Soc. Sci. Ed.), 12(1):127-131 (in Chinese).
[33]Zeng, X.P., Wang, P.J., 2009. Design of Low-Power Complementary Pass-Transistor and Ternary Adder Based on Multi-valued Switch-Signal Theory. IEEE 8th Int. Conf. on ASIC, p.851-854.
[34]Zhang, W.C., Wu, N.J., 2008. Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs. Electron. Lett., 44(16):968-969.
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